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rev. 2.1 february 2000 1/164 st72311r, st72511r, st72512r, st72532r 8-bit mcu with nested interrupts, eeprom, adc, 16-bit timers, 8-bit pwm art, spi, sci, can interfaces datasheet n memories 16k to 60k bytes program memory (rom,otp and eprom) with read-out protection 256 bytes e 2 prom data memory (only on st72532r4) 1024 to 2048 bytes ram n clock, reset and supply management enhanced reset system low voltage supply supervisor clock sources: crystal/ceramic resonator os- cillator or external clock beep and clock-out capability 4 power saving modes: halt, active-halt, wait and slow n interrupt management nested interrupt controller 13 interrupt vectors plus trap and reset 15 external interrupt lines (on 4 vectors) tli dedicated top level interrupt pin n 48 i/o ports 48 multifunctional bidirectional i/o lines 32 alternate function lines 12 high sink outputs n 5 timers configurable watchdog timer real time clock timer one 8-bit auto-reload timer with 4 independ- ent pwm output channels, 2 input captures, output compares and external clock with event detector (except on st725x2r4) two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, pwm and pulse generator modes n 3 communications interfaces spi synchronous serial interface sci asynchronous serial interface can interface (except on st72311rx) n 1 analog peripheral 8-bit adc with 8 input channels n instruction set 8-bit data manipulation 63 basic instructions 17 main addressing modes 8 x 8 unsigned multiply instruction true bit manipulation n development tools full hardware/software development package device summary note 1. see section 12.3.1 on page 133 for more information on v dd versus f osc . tqfp64 14 x 14 features st72511r9 st72511r7 st72511r6 st72311r9 st72311r7 st72311r6 st72512r4 st72532r4 program memory - bytes 60k 48k 32k 60k 48k 32k 16k 16k ram (stack) - bytes 2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256) 1024 (256) eeprom - bytes - - - --- -256 peripherals watchdog, two 16-bit timers, 8-bit pwm art, spi, sci, can, adc watchdog, two 16-bit timers, 8-bit pwm art, spi, sci, adc watchdog, two 16-bit timers, spi, sci, can, adc operating supply 3.0v to 5.5v 3.0 to 5.5v 1) cpu frequency 2 to 8 mhz (with 4 to 16 mhz oscillator) 2 to 4 mhz 1) operating temperature -40 c to +85 c (-40 c to +105/125 c optional) packages tqfp64 1
table of contents 164 2/164 2 1 general description . . . . . . ................................................ 6 1.1 introduction . ....................................................... 6 1.2 pin description . . . . . . ................................................ 7 1.3 register & memory map . . . . . . . . . . . . . . . .............................. 11 2 eprom program memory . . . . . . . ........................................... 15 3 data eeprom . . . . . . . . . .................................................... 16 3.1 introduction . ...................................................... 16 3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 16 3.3 memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 17 3.4 power saving modes . . . . . . ......................................... 18 3.5 access error handling . . . . . . . . . . . ................................. 18 3.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 19 4 central processing unit . . ............................................... 20 4.1 introduction . ...................................................... 20 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 20 4.3 cpu registers . . . . . . . . . . . . . . . . . . . . . ................................. 20 5 supply, reset and clock management . . . . ................................ 23 5.1 low voltage detector (lvd) . . . . . . . . ................................ 24 5.2 reset sequence manager (rsm) . . . . . ................................ 25 5.2.1 introduction . . . . . . . . . . . . ........................................... 25 5.2.2 asynchronous external reset pin . . . ............................. .... 26 5.2.3 internal low voltage detection reset . . . . . . . . . . . . . . . . . . . . . . ........... 26 5.2.4 internal watchdog reset . . . ........................................ 26 5.3 low consumption oscillator . . . . . .................................. 27 6 interrupts . . ......................... .................................... 28 6.1 introduction . ...................................................... 28 6.2 masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 concurrent & nested management . . . . . . . . . . . . . .................... 30 6.5 interrupt register description . . . ............................. .... 31 7 power saving modes . . . . . . . . . . ........................................... 34 7.1 introduction . ...................................................... 34 7.2 slow mode . . . . . . . . . . . . . . ........................................... 34 7.3 wait mode . . . . . . . . . . . ............................................... 35 7.4 active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.1 active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.2 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . ........................................ 38 8.1 introduction . ...................................................... 38 8.2 functional description . . . . ........................................ 38 8.2.1 input modes . . .................................................... 38 8.2.2 output modes . . . . . . . . . . . . . ........................................ 38 8.2.3 alternate functions . . . . . . ........................................... 38
table of contents 3/164 3 8.3 i/o port implementation . . . . ........................................ 41 8.4 low power modes . . . . . . . . . . . . . . . . . ................................. 42 8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . ................................. 42 8.5.1 register description . . . . . ........................................... 43 9 miscellaneous registers . . . . . . . . . . . . . . .................................. 45 9.1 i/o port interrupt sensitivity . . . . . . ................................ 45 9.2 i/o port alternate functions . . . . . .................................. 45 9.3 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 on-chip peripherals . . . . . . ............................................... 49 10.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . ........................... 49 10.1.1 introduction . . . . . . . . . . . . . . . ........................................ 49 10.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 49 10.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.1.4 hardware watchdog option . . ........................................ 50 10.1.5 low power modes . . ............................................... 50 10.1.6 interrupts . . ....................................................... 50 10.1.7 register description . ............................................... 50 10.2 main clock controller with real time clock timer (mcc/rtc) . . . . . . . 52 10.2.1 programmable cpu clock prescaler . . . . . . . . . . . . . . . . . . . . ............... 52 10.2.2 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.2.3 real time clock timer (rtc) ........................................ 52 10.2.4 register description . ............................................... 53 10.2.5 low power modes . . . . . . . . . ........................................ 53 10.2.6 interrupts . . ....................................................... 53 10.3 pwm auto-reload timer (art) . . . . . . . ................................ 54 10.3.1 introduction . . . . . . . . . . . . . . . ........................................ 54 10.3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.3.3 register description . ............................................... 58 10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 61 10.4.1 introduction . . . . . . . . . . . . . . . ........................................ 61 10.4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 61 10.4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.4.4 low power modes . . . . . . . . . ........................................ 73 10.4.5 interrupts . . . . . . . . . . . . . ........................................... 73 10.4.6 summary of timer modes . . . . . . . . . . ............................. .... 73 10.4.7 register description . ............................................... 74 10.5 serial peripheral interface (spi) . .................................. 79 10.5.1 introduction . . . . . . . . . . . . . . . ........................................ 79 10.5.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 79 10.5.3 general description . . . . . . . . . ........................................ 79 10.5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.5.5 low power modes . . ............................................... 88 10.5.6 interrupts . . . . . . . . . . . . . ........................................... 88 10.5.7 register description . ............................................... 89
st72311r, st72511r, st72512r, st72532r 4/164 10.6 serial communications interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.6.1 introduction . . . . . . . . . . . . . . . ........................................ 92 10.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ 92 10.6.3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .................... 92 10.6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.6.5 low power modes . . ............................................... 99 10.6.6 interrupts . . ....................................................... 99 10.6.7 register description . .............................................. 100 10.7 controller area network (can) . . . ................................ 104 10.7.1 introduction . . . . . . . . . . . . . . . ....................................... 104 10.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 105 10.7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.7.4 register description . .............................................. 111 10.8 8-bit a/d converter (adc) .......................................... 121 10.8.1 introduction . . . . . . . . . . . . . . . ....................................... 121 10.8.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 121 10.8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.8.4 low power modes . . . . . . . . . ....................................... 122 10.8.5 interrupts . . ...................................................... 122 10.8.6 register description . .............................................. 123 11 instruction set . . . . . . . . . . . . . . . . . . . . . . . . ................................ 125 11.1 st7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.1.1 inherent ...... ................................. .................. 126 11.1.2 immediate . . ..................................................... 126 11.1.3 direct . . . . . . . . . . . . . . . . .......................................... 126 11.1.4 indexed (no offset, short, long) . . . . . . ............................... 126 11.1.5 indirect (short, long) . . . . . . . . . . . . . . . . . . . . .......................... 126 11.1.6 indirect indexed (short, long) ....................................... 127 11.1.7 relative mode (direct, indirect) . . . . . . ................................ 127 11.2 instruction groups . . . . . . . . . . . . . . . . . . ............................. 128 12 electrical characteristics . . . . ........................................ 131 12.1 parameter conditions . . . . . . . . . . . . . . . . ............................. 131 12.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.1.2 typical values . . . . . . . . . . . . . . . . . . . . . ............................... 131 12.1.3 typical curves . . . . . . . . . . . . . ....................................... 131 12.1.4 loading capacitor . . . . . . . . . . ....................................... 131 12.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 12.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.2.1 voltage characteristics . . . . . . . . . . . . ................................ 132 12.2.2 current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 12.2.3 thermal characteristics . . . . . . . . . . . . . . . ............................. 132 12.3 operating conditions . . . . . . . . . . ................................... 133 12.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 133 12.3.2 operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . ....... 134 12.4 supply current characteristics . . . ............................... 135 12.4.1 run and slow modes . . . . . . . . . . . . . . . . . . . . . . . . . ................... 135 12.4.2 wait and slow wait modes . . . . . ................................. 136
st72311r, st72511r, st72512r, st72532r 5/164 12.4.3 halt and active-halt modes . . . . . ............................... 137 12.4.4 supply and clock managers . . . . . . ................................... 137 12.4.5 on-chip peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 12.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . .......... 138 12.5.1 general timings . . . .............................................. 138 12.5.2 external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.5.3 crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 12.6 memory characteristics . . . ....................................... 139 12.6.1 ram and hardware registers . . . . . . . ................................ 139 12.6.2 eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 12.6.3 eprom program memory . . . ....................................... 139 12.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 12.7.1 functional ems . . . . . . . . . . . . . . . . . . ................................ 140 12.7.2 absolute electrical sensitivity . ....................................... 141 12.7.3 esd pin protection strategy . . . . . . . . . ................................ 143 12.8 i/o port pin characteristics ....................................... 145 12.8.1 general characteristics . . . . . ....................................... 145 12.8.2 output driving current . . . . . . ....................................... 146 12.9 control pin characteristics . . . . . ................................. 147 12.9.1 asynchronous reset pin .......................................... 147 12.9.2 vpp pin . . . . . . . . . . . . . . . . . . . . . . . . . ............................... 147 12.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 148 12.10.1watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... 148 12.10.28-bit pwm-art auto-reload timer . ................................. 148 12.10.316-bit timer . . . . . . . . . . . . . . . . . . . . . ................................ 148 12.11 communications interface characteristics . . . . . . . . . . . . . . . . . . . . . . . 149 12.11.1spi - serial peripheral interface . . . . . . . . . . . . .......................... 149 12.11.2sci - serial communications interface . . . . . . . . . . . . . . . . . . . . . . .......... 151 12.11.3can - controller area network interface . . . . . . . . . . . . ................... 151 12.12 8-bit adc characteristics . . . . . . . . ................................. 152 13 package characteristics . . . . . . ........................................ 154 13.1 package mechanical data . . . . . . . . . . . . ............................. 154 13.2 thermal characteristics . . . . . . . . . . . ............................... 155 13.3 soldering and glueability information . . . . . . . . . . . . . . . . . . . . . ....... 156 13.4 package/socket footprint proposal . . . . . . . . . . . ................... 157 14 device configuration and ordering information . . . . . . . . . . . . . . . . . . . . . . . 158 14.1 option bytes . . . ................................. .................. 158 14.2 device ordering information and transfer of customer code . . . . 159 14.3 development tools . . . . . . . . . . . . . . . . . . . . . .......................... 161 15 st7 generic application note . . . ....................................... 162 16 summary of changes . .................................................. 163
st72311r, st72511r, st72512r, st72532r 6/164 1 general description 1.1 introduction the st72311r, st72511r, st72512r and st72532r devices are members of the st7 mi- crocontroller family. they can be grouped as fol- lows: st725xxr devices are designed for mid-range applications with a can bus interface (controller area network) st72311r devices target the same range of ap- plications but without can interface. all devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. under software control, all devices can be placed in wait, slow, active-halt or halt mode, reducing power consumption when the application is in idle or standby state. the enhanced instruction set and addressing modes of the st7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. in addition to standard 8-bit data management, all st7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. figure 1. device block diagram 8-bit core alu address and data bus osc1 v pp control program (16k - 60k bytes) v ss reset port f pf7:0 (8-bit) timer a beep port a ram (1024, 2048 bytes) port c 8-bit adc v dda v ssa port b pb7:0 (8-bit) pwm art port e can pe7:0 (8-bit) sci timer b pa7:0 (8-bit) port d pd7:0 (8-bit) spi pc7:0 (8-bit) v dd eeprom (256 bytes) watchdog tli osc lvd osc2 memory mcc/rtc 4
st72311r, st72511r, st72512r, st72532r 7/164 1.2 pin description figure 2. 64-pin tqfp package pinout v dda v ssa v dd_3 v ss_3 mco / pf0 beep / pf1 pf2 ocmp2_a / pf3 ocmp1_a / pf4 icap2_a / pf5 icap1_a / (hs) pf6 extclk_a / (hs) pf7 ain4 / pd4 ain5 / pd5 ain6 / pd6 ain7 / pd7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ei2 ei3 ei0 ei1 pwm3 / pb0 pwm2 / pb1 pwm1 / pb2 pwm0 / pb3 artclk / pb4 pb5 pb6 pb7 ain0 / pd0 ain1 / pd1 ain2 / pd2 ain3 / pd3 (hs) pe4 (hs) pe5 (hs) pe6 (hs) pe7 pa1 pa0 pc7 / ss pc6 / sck pc5 / mosi pc4 / miso pc3 (hs) / icap1_b pc2 (hs) / icap2_b pc1 / ocmp1_b pc0 / ocmp2_b v ss_0 v dd_0 v ss_1 v dd_1 pa3 pa2 v dd _2 osc1 osc2 v ss _2 tli nc reset v pp pa7 (hs) pa6 (hs) pa5 (hs) pa4 (hs) pe3 / canrx pe2 / cantx pe1 / rdi pe0 / tdo (hs) 20ma high sink capability eix associated external interrupt vector 5
st72311r, st72511r, st72512r, st72532r 8/164 pin description (cont'd) for external pin connection guidelines, refer to section 12 oelectrical characteristicso on page 131. legend / abbreviations for table 1 : type: i = input, o = output, s = supply input level: a = dedicated analog input in/output level: c = cmos 0.3v dd /0.7v dd , c t = cmos 0.3v dd /0.7v dd with input trigger output level: hs = 20ma high sink (on n-buffer only) port and control configuration: input: float = floating, wpu = weak pull-up, int = interrupt 1) , ana = analog output: od = open drain 2) , pp = push-pull refer to section 8 oi/o portso on page 38 for more details on the software configuration of the i/o ports. the reset configuration of each pin is shown in bold. this configuration is valid as long as the device is in reset state. table 1. device pin description pin n pin name type level port main function (after reset) alternate function tqfp64 input output inpu t output float wpu int ana od pp 1 pe4 (hs) i/o c t hs x x x x port e4 2 pe5 (hs) i/o c t hs x x x x port e5 3 pe6 (hs) i/o c t hs x x x x port e6 4 pe7 (hs) i/o c t hs x x x x port e7 5 pb0/pwm3 i/o c t x ei2 x x port b0 pwm output 3 6 pb1/pwm2 i/o c t x ei2 x x port b1 pwm output 2 7 pb2/pwm1 i/o c t x ei2 x x port b2 pwm output 1 8 pb3/pwm0 i/o c t x ei2 x x port b3 pwm output 0 9 pb4/artclk i/o c t x ei3 x x port b4 pwm-art external clock 10 pb5 i/o c t x ei3 x x port b5 11 pb6 i/o c t x ei3 x x port b6 12 pb7 i/o c t x ei3 x x port b7 13 pd0/ain0 i/o c t x x x x x port d0 adc analog input 0 14 pd1/ain1 i/o c t x x x x x port d1 adc analog input 1 15 pd2/ain2 i/o c t x x x x x port d2 adc analog input 2 16 pd3/ain3 i/o c t x x x x x port d3 adc analog input 3 17 pd4/ain4 i/o c t x x x x x port d4 adc analog input 4 18 pd5/ain5 i/o c t x x x x x port d5 adc analog input 5 19 pd6/ain6 i/o c t x x x x x port d6 adc analog input 6 20 pd7/ain7 i/o c t x x x x x port d7 adc analog input 7 21 v dda s analog power supply voltage 22 v ssa s analog ground voltage 23 v dd_3 s digital main supply voltage 6
st72311r, st72511r, st72512r, st72532r 9/164 24 v ss_3 s digital ground voltage 25 pf0/mco i/o c t x ei1 x x port f0 main clock output (f osc /2) 26 pf1/beep i/o c t x ei1 x x port f1 beep signal output 27 pf2 i/o c t x ei1 x x port f2 28 pf3/ocmp2_a i/o c t x x x x port f3 timer a output compare 2 29 pf4/ocmp1_a i/o c t x x x x port f4 timer a output compare 1 30 pf5/icap2_a i/o c t x x x x port f5 timer a input capture 2 31 pf6 (hs)/icap1_a i/o c t hs x x x x port f6 timer a input capture 1 32 pf7 (hs)/extclk_a i/o c t hs x x x x port f7 timer a external clock source 33 v dd_0 s digital main supply voltage 34 v ss_0 s digital ground voltage 35 pc0/ocmp2_b i/o c t x x x x port c0 timer b output compare 2 36 pc1/ocmp1_b i/o c t x x x x port c1 timer b output compare 1 37 pc2 (hs)/icap2_b i/o c t hs x x x x port c2 timer b input capture 2 38 pc3 (hs)/icap1_b i/o c t hs x x x x port c3 timer b input capture 1 39 pc4/miso i/o c t x x x x port c4 spi master in / slave out data 40 pc5/mosi i/o c t x x x x port c5 spi master out / slave in data 41 pc6/sck i/o c t x x x x port c6 spi serial clock 42 pc7/ss i/o c t x x x x port c7 spi slave select (active low) 43 pa0 i/o c t x ei0 x x port a0 44 pa1 i/o c t x ei0 x x port a1 45 pa2 i/o c t x ei0 x x port a2 46 pa3 i/o c t x ei0 x x port a3 47 v dd_1 s digital main supply voltage 48 v ss_1 s digital ground voltage 49 pa4 (hs) i/o c t hs x x x x port a4 50 pa5 (hs) i/o c t hs x x x x port a5 51 pa6 (hs) i/o c t hs x t port a6 52 pa7 (hs) i/o c t hs x t port a7 53 v pp i must be tied low in user mode. in programming mode when available, this pin acts as the pro- gramming voltage input v pp . 54 reset i/o c x x top priority non maskable interrupt (active low) 55 nc not connected 56 nmi i c t x non maskable interrupt input pin 57 v ss_3 s digital ground voltage 58 osc2 3) i/o external clock mode input pull-up or crystal/ce- ramic resonator oscillator inverter output 59 osc1 3) i external clock input or crystal/ceramic resona- tor oscillator inverter input 60 v dd_3 s digital main supply voltage pin n pin name type level port main function (after reset) alternate function tqfp64 input output inpu t output float wpu int ana od pp
st72311r, st72511r, st72512r, st72532r 10/164 notes : 1. in the interrupt input column, aeixo defines the associated external interrupt vector. if the weak pull-up column (wpu) is merged with the interrupt column (int), then the i/o configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. in the open drain output column, ato defines a true open drain i/o (p-buffer and protection diode to v dd are not implemented). see section 8 oi/o portso on page 38 and section 12.8 oi/o port pin char- acteristicso on page 145 for more details. 3. osc1 and osc2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator see section 1.2 opin descriptiono on page 7 and section 12.5 oclock and timing character- isticso on page 138 for more details. 61 pe0/tdo i/o c t x x x x port e0 sci transmit data out 62 pe1/rdi i/o c t x x x x port e1 sci receive data in 63 pe2/cantx i/o c t x port e2 can transmit data output 64 pe3/canrx i/o c t x x x x port e3 can receive data input pin n pin name type level port main function (after reset) alternate function tqfp64 input output inpu t output float wpu int ana od pp
st72311r, st72511r, st72512r, st72532r 11/164 1.3 register & memory map as shown in the figure 3, the mcu is capable of addressing 64k bytes of memories and i/o regis- ters. the available memory locations consist of 128 bytes of register location, up to 2kbytes of ram, up to 256 bytes of data eeprom and up to 60kbytes of user program memory. the ram space includes up to 256 bytes for the stack from 0100h to 01ffh. the highest address bytes contain the user reset and interrupt vectors. figure 3. memory map 0000h 1024 bytes ram program memory (60k, 48k, 32k, 16k bytes) interrupt & reset vectors hw registers 0bffh 0080h 007fh 0d00h 0fffh reserved 2048 bytes ram (see table 2) 1000h ffdfh ffe0h ffff h (see table 7 on page 32) 0c00h 0cffh optional eeprom (256 bytes) 0880h reserved 087fh short addressing ram (zero page) stack (256 bytes) 16-bit addressing ram 0100h 01ffh 047fh 0080h 0200h 00ffh or 067fh or 087fh 1536 bytes ram 16 kbytes 4000h 1000h 48 kbytes c000h 8000h 32 kbytes 60 kbytes ffff h
st72311r, st72511r, st72512r, st72532r 12/164 table 2. hardware register map address block register label register name reset status remarks 0000h 0001h 0002h port a padr paddr paor port a data register port a data direction register port a option register 00h 1) 00h 00h r/w r/w r/w 2) 0003h reserved area (1 byte) 0004h 0005h 0006h port c pcdr pcddr pcor port c data register port c data direction register port c option register 00h 1) 00h 00h r/w r/w r/w 0007h reserved area (1 byte) 0008h 0009h 000ah port b pbdr pbddr pbor port b data register port b data direction register port b option register 00h 1) 00h 00h r/w r/w r/w 000bh reserved area (1 byte) 000ch 000dh 000eh port e pedr peddr peor port e data register port e data direction register port e option register 00h 1) 00h 00h r/w r/w 2) r/w 2) 000fh reserved area (1 byte) 0010h 0011h 0012h port d pddr pdddr pdor port d data register port d data direction register port d option register 00h 1) 00h 00h r/w r/w r/w 0013h reserved area (1 byte) 0014h 0015h 0016h port f pfdr pfddr pfor port f data register port f data direction register port f option register 00h 1) 00h 00h r/w r/w r/w 0017h to 001fh reserved area (9 bytes) 0020h miscr1 miscellaneous register 1 00h r/w 0021h 0022h 0023h spi spidr spicr spisr spi data i/o register spi control register spi status register xxh 0xh 00h r/w r/w read only 0024h 0025h 0026h 0027h itc ispr0 ispr1 ispr2 ispr3 interrupt software priority register 0 interrupt software priority register 1 interrupt software priority register 2 interrupt software priority register 3 ffh ffh ffh ffh r/w r/w r/w r/w 0028h reserved area (1 byte) 0029h mcc mccsr main clock control / status register 01h r/w
st72311r, st72511r, st72512r, st72532r 13/164 002ah 002bh watchdog wdgcr wdgsr watchdog control register watchdog status register 7fh 000x 000x r/w r/w 002ch eeprom eecsr data eeprom control/status register 00h r/w 002dh to 0030h reserved area (4 bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh timer a tacr2 tacr1 tasr taic1hr taic1lr taoc1hr taoc1lr tachr taclr taachr taaclr taic2hr taic2lr taoc2hr taoc2lr timer a control register 2 timer a control register 1 timer a status register timer a input capture 1 high register timer a input capture 1 low register timer a output compare 1 high register timer a output compare 1 low register timer a counter high register timer a counter low register timer a alternate counter high register timer a alternate counter low register timer a input capture 2 high register timer a input capture 2 low register timer a output compare 2 high register timer a output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0040h miscr2 miscellaneous register 2 00h r/w 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh timer b tbcr2 tbcr1 tbsr tbic1hr tbic1lr tboc1hr tboc1lr tbchr tbclr tbachr tbaclr tbic2hr tbic2lr tboc2hr tboc2lr timer b control register 2 timer b control register 1 timer b status register timer b input capture 1 high register timer b input capture 1 low register timer b output compare 1 high register timer b output compare 1 low register timer b counter high register timer b counter low register timer b alternate counter high register timer b alternate counter low register timer b input capture 2 high register timer b input capture 2 low register timer b output compare 2 high register timer b output compare 2 low register 00h 00h xxh xxh xxh 80h 00h ffh fch ffh fch xxh xxh 80h 00h r/w r/w read only read only read only r/w r/w read only read only read only read only read only read only r/w r/w 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h sci scisr scidr scibrr scicr1 scicr2 scierpr scietpr sci status register sci data register sci baud rate register sci control register 1 sci control register 2 sci extended receive prescaler register reserved area sci extended transmit prescaler register c0h xxh 00xx xxxx xxh 00h 00h 00h read only r/w r/w r/w r/w r/w r/w address block register label register name reset status remarks
st72311r, st72511r, st72512r, st72532r 14/164 legend : x=undefined, r/w=read/write notes : 1. the contents of the i/o port dr registers are readable only in output configuration. in input configura- tion, the values of the i/o pins are returned instead of the dr register contents. 2. the bits associated with unavailable pins must always keep their reset value. 0058h 0059h reserved area (2 bytes) 005ah 005bh 005ch 005dh 005eh 005fh 0060h to 006fh can canisr canicr cancsr canbrpr canbtr canpsr can interrupt status register can interrupt control register can control / status register can baud rate prescaler register can bit timing register can page selection register first address to last address of can page x 00h 00h 00h 00h 23h 00h r/w r/w r/w r/w r/w r/w see can description 0070h 0071h adc adcdr adccsr data register control/status register xxh 00h read only r/w 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h pwm art pwmdcr3 pwmdcr2 pwmdcr1 pwmdcr0 pwmcr artcsr artcar artarr pwm ar timer duty cycle register 3 pwm ar timer duty cycle register 2 pwm ar timer duty cycle register 1 pwm ar timer duty cycle register 0 pwm ar timer control register auto-reload timer control/status register auto-reload timer counter access register auto-reload timer auto-reload register 00h 00h 00h 00h 00h 00h 00h 00h r/w r/w r/w r/w r/w r/w r/w r/w 007ah to 007fh reserved area (6 bytes) address block register label register name reset status remarks
st72311r, st72511r, st72512r, st72532r 15/164 2 eprom program memory the program memory of the otp and eprom de- vices can be programmed with eprom program- ming tools available from stmicroelectronics eprom erasure eprom devices are erased by exposure to high intensity uv light admitted through the transparent window. this exposure discharges the floating gate to its initial state through induced photo cur- rent. it is recommended that the eprom devices be kept out of direct sunlight, since the uv content of sunlight can be sufficient to cause functional fail- ure. extended exposure to room level fluorescent lighting may also cause erasure. an opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. covering the window also reduces i dd in power-saving modes due to photo-diode leakage currents.
st72311r, st72511r, st72512r, st72532r 16/164 3 data eeprom 3.1 introduction the electrically erasable programmable read only memory can be used as a non volatile back- up for storing data. using the eeprom requires a basic access protocol described in this chapter. 3.2 main features n up to 16 bytes programmed in the same cycle n eeprom mono-voltage (charge pump) n chained erase and programming cycles n internal control of the global programming cycle duration n end of programming cycle interrupt flag n wait mode management figure 4. eeprom block diagram eecsr eeprom interrupt falling edge high voltage pump ie lat 0 0000 pgm eeprom reserved detector eeprom memory matrix (1 row = 16 x 8 bits) address decoder data multiplexer 16 x 8 bits data latches row decoder data bus 4 4 4 128 128 address bus
st72311r, st72511r, st72512r, st72532r 17/164 data eeprom (cont'd) 3.3 memory access the data eeprom memory read/write access modes are controlled by the lat bit of the eep- rom control/status register (eecsr). the flow- chart in figure 5 describes these different memory access modes. read operation (lat=0) the eeprom can be read as a normal rom loca- tion when the lat bit of the eecsr register is cleared. in a read cycle, the byte to be accessed is put on the data bus in less than 1 cpu clock cycle. this means that reading data from eeprom takes the same time as reading data from eprom, but this memory cannot be used to exe- cute machine code. write operation (lat=1) to access the write mode, the lat bit has to be set by software (the pgm bit remains cleared). when a write access to the eeprom area occurs, the value is latched inside the 16 data latches ac- cording to its address. when pgm bit is set by the software, all the previ- ous bytes written in the data latches (up to 16) are programmed in the eeprom cells. the effective high address (row) is determined by the last eep- rom write sequence. to avoid wrong program- ming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four least significant bits of the address can change. at the end of the programming cycle, the pgm and lat bits are cleared simultaneously, and an inter- rupt is generated if the ie bit is set. the data eep- rom interrupt request is cleared by hardware when the data eeprom interrupt vector is fetched. note : care should be taken during the program- ming cycle. writing to the same memory location will over-program the memory (logical and be- tween the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of lat bit. it is not possible to read the latched data. this note is ilustrated by the figure 6. figure 5. data eeprom programming flowchart read mode lat=0 pgm=0 write mode lat=1 pgm=0 read bytes in eeprom area write up to 16 bytes in eeprom area (with the same 12 msb of the address) start programming cycle lat=1 pgm=1 (set by software) lat interrupt generation if ie=1 0 1 cleared by hardware
st72311r, st72511r, st72512r, st72532r 18/164 data eeprom (cont'd) 3.4 power saving modes wait mode the data eeprom can enter wait mode on ex- ecution of the wfi instruction of the microcontrol- ler. the data eeprom will immediately enter this mode if there is no programming in progress, otherwise the data eeprom will finish the cycle and then enter wait mode. halt mode the data eeprom immediatly enters halt mode if the microcontroller executes the halt in- struction. therefore the eeprom will stop the function in progress, and data may be corrupted. 3.5 access error handling if a read access occurs while lat=1, then the data bus will not be driven. if a write access occurs while lat=0, then the data on the bus will not be latched. if a programming cycle is interrupted (by software/ reset action), the memory data will not be guar- anteed. figure 6. data eeprom programming cycle lat erase cycle write cycle pgm t prog read operation not possible write of data latches read operation possible internal programming voltage eeprom interrupt
st72311r, st72511r, st72512r, st72532r 19/164 data eeprom (cont'd) 3.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7:3 = reserved, forced by hardware to 0. bit 2 = ie interrupt enable this bit is set and cleared by software. it enables the data eeprom interrupt capability when the pgm bit is cleared by hardware. the interrupt request is automatically cleared when the software enters the interrupt routine. 0: interrupt disabled 1: interrupt enabled bit 1 = lat latch access transfer this bit is set by software. it is cleared by hard- ware at the end of the programming cycle. it can only be cleared by software if pgm bit is cleared. 0: read mode 1: write mode bit 0 = pgm programming control and status this bit is set by software to begin the programming cycle. at the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ite bit is set. 0: programming finished or not yet started 1: programming cycle is in progress note : if the pgm bit is cleared during the program- ming cycle, the memory data is not guaranteed table 3. data eeprom register map and reset values 70 00000ielatpgm address (hex.) register label 76543210 002ch eecsr reset value 00000 ie 0 rwm 0 pgm 0
st72311r, st72511r, st72512r, st72532r 20/164 4 central processing unit 4.1 introduction this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 main features n enable executing 63 basic instructions n fast 8-bit by 8-bit multiply n 17 main addressing modes (with indirect addressing mode) n two 8-bit index registers n 16-bit stack pointer n low power halt and wait modes n priority maskable hardware interrupts n non-maskable software/hardware interrupts 4.3 cpu registers the 6 cpu registers shown in figure 7 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose reg- ister used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. index registers (x and y) these 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (the cross-assembler generates a precede instruction (pre) to indicate that the fol- lowing instruction refers to the y register.) the y register is not affected by the interrupt auto- matic procedures. program counter (pc) the program counter is a 16-bit register containing the address of the next instruction to be executed by the cpu. it is made of two 8-bit registers pcl (program counter low which is the lsb) and pch (program counter high which is the msb). figure 7. cpu registers accumulator x index register y index register stack pointer conditio n code register program counter 70 1c 1i1hi0nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 87 0 reset value = stack higher address reset value = 1x 11x1xx reset value = xxh reset value = xxh reset value = xxh x = undefined value
st72311r, st72511r, st72512r, st72532r 21/164 central processing unit (cont'd) condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. this register can also be handled by the push and pop in- structions. these bits can be individually tested and/or con- trolled by specific instructions. arithmetic management bits bit 4 = h half carry . this bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the alu during an add or adc instructions. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: an half carry has occurred. this bit is tested using the jrh or jrnh instruc- tion. the h bit is useful in bcd arithmetic subrou- tines. bit 2 = n negative . this bit is set and cleared by hardware. it is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. it's a copy of the re- sult 7 th bit. 0: the result of the last operation is positive or null. 1: the result of the last operation is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instruc- tions. bit 1 = z zero . this bit is set and cleared by hardware. this bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow. this bit is set and cleared by hardware and soft- ware. it indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf instructions and tested by the jrc and jrnc instructions. it is also affected by the abit test and brancho, shift and rotate instructions. interrupt management bits bit 5,3 = i1, i0 interrupt. the combination of the iand i0 bits gives the cur- rent interrupt software priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ixspr). they can be also set/ cleared by software with the rim, sim, iret, halt, wfi and push/pop instructions. see the interrupt management chapter for more details. 70 11i1hi0nz c interrupt software priority i1 i0 level 0 (main) 1 0 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1
st72311r, st72511r, st72512r, st72532r 22/164 central processing unit (cont'd) stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register which is al- ways pointing to the next free location in the stack. it is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see figure 8). since the stack is 256 bytes deep, the 8 most sig- nificant bits are forced by hardware. following an mcu reset, or after a reset stack pointer instruc- tion (rsp), the stack pointer contains its reset val- ue (the sp7 to sp0 bits are set) which is the stack higher address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld in- struction. note: when the lower limit is exceeded, the stack pointer wraps around to the stack upper limit, with- out indicating the stack overflow. the previously stored information is then overwritten and there- fore lost. the stack also wraps in case of an under- flow. the stack is used to save the return address dur- ing a subroutine call and the cpu context during an interrupt. the user may also directly manipulate the stack by means of the push and pop instruc- tions. in the case of an interrupt, the pcl is stored at the first location pointed to by the sp. then the other registers are stored in the next locations as shown in figure 8 when an interrupt is received, the sp is decre- mented and the context is pushed on the stack. on return from interrupt, the sp is incremented and the context is popped from the stack. a subroutine call occupies two locations and an in- terrupt five locations in the stack area. figure 8. stack manipulation example 15 8 00000001 70 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 pch pcl sp pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp pcl pch x a cc pch pcl sp sp y call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h
st72311r, st72511r, st72512r, st72532r 23/164 5 supply, reset and clock management the st72311r, st72511r, st72512r and st72532r microcontrollers include a range of util- ity features for securing the application in critical situations (for example in case of a power brown- out), and reducing the number of external compo- nents. an overview is shown in figure 9. main features n main supply low voltage detection (lvd) n reset manager (rsm) n low consumption resonator oscillator figure 9. clock, reset, option and supply management overview f osc low voltage detector (lvd) from watchdog peripheral osc2 osc1 reset v dd v ss oscillator reset to main clock controller
st72311r, st72511r, st72512r, st72532r 24/164 5.1 low voltage detector (lvd) to allow the integration of power management features in the application, the low voltage detec- tor function (lvd) generates a static reset when the v dd supply voltage is below a v it- reference value. this means that it secures the power-up as well as the power-down keeping the st7 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run- ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: v it+ when v dd is rising v it- when v dd is falling the lvd function is illustrated in figure 10. provided the minimum v dd value (guaranteed for the oscillator frequency) is below v it- , the mcu can only be in two modes: under full software control in static safe reset in these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. notes : the lvd allows the device to be used without any external reset circuitry. the lvd is an optional function which can be se- lected when ordering the device (ordering informa- tion). figure 10. low voltage detector vs reset v dd v it+ reset v it- v hys
st72311r, st72511r, st72512r, st72532r 25/164 5.2 reset sequence manager (rsm) 5.2.1 introduction the reset sequence manager includes three re- set sources as shown in figure 12: n external reset source pulse n internal lvd reset (low voltage detection) n internal watchdog reset these sources act on the reset pin and it is al- ways kept low during the delay phase. the reset service routine vector is fixed at ad- dresses fffeh-ffffh in the st7 memory map. the basic reset sequence consists of 3 phases as shown in figure 11: n delay depending on the reset source n 4096 cpu clock cycle delay n reset vector fetch the 4096 cpu clock cycle delay allows the oscil- lator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. figure 11. reset sequence phases figure 12. reset block diagram reset delay internal reset 4096 clock cycles fetch vector f cpu counter reset r on v dd watchdog reset lvd reset internal reset
st72311r, st72511r, st72512r, st72532r 26/164 reset sequence manager (cont'd) 5.2.2 asynchronous external reset pin the reset pin is both an input and an open-drain output with integrated r on weak pull-up resistor. this pull-up has no fixed value but varies in ac- cordance with the input voltage. it can be pulled low by external circuitry to reset the device. see electrical characteristics section for more details. a reset signal originating from an external source must have a duration of at least t h(rstl)in in order to be recognized as shown in figure 13. this detection is asynchronous and therefore the mcu can enter reset state even in halt mode. the reset pin is an asynchronous signal which plays a major role in ems performance. in a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteris- tics section. 5.2.3 internal low voltage detection reset two different reset sequences caused by the in- ternal lvd circuitry can be distinguished: n power-on reset n voltage drop reset the device reset pin acts as an output that is pulled low when v dd st72311r, st72511r, st72512r, st72532r 27/164 5.3 low consumption oscillator the f osc main clock of the st7 can be generated by two different source types: n an external source n a crystal or ceramic resonator oscillators the associated hardware configuration are shown in table 4. refer to the electrical characteristics section for more details. external clock source in this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc1 pin while the osc2 pin is tied to ground. crystal/ceramic oscillator this oscillator (based on constant current source) is optimized in terms of consumption and has the advantage of producing a very accurate rate on the main clock of the st7. when using this oscillator, the resonator and the load capacitances have to be connected as shown in table 4 and have to be mounted as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. this oscillator is not stopped during the reset phase to avoid losing time in the oscillator start-up phase. these oscillators are not stopped during the reset phase to avoid losing time in the oscillator start-up phase. table 4. st7 clock sources hardware configuration external clock crystal/ceramic resonators osc1 osc2 external st7 source v dd r obp osc1 osc2 load capacitors st7 c l2 c l1
st72311r, st72511r, st72512r, st72532r 28/164 6 interrupts 6.1 introduction the st7 enhanced interrupt management pro- vides the following features: n hardware interrupts n software interrupt (trap) n nested or concurrent interrupt management with flexible interrupt priority and level management: up to 4 software programmable nesting levels up to 16 interrupt vectors fixed by hardware 3 non maskable events: tli, reset, trap this interrupt management is based on: bit 5 and bit 3 of the cpu cc register (i1:0), interrupt software priority registers (isprx), fixed interrupt vector addresses located at the high addresses of the memory map (ffe0h to ffffh) sorted by hardware priority order. this enhanced interrupt controller guarantees full upward compatibility with the standard (not nest- ed) st7 interrupt controller. 6.2 masking and processing flow the interrupt masking is managed by the i1 and i0 bits of the cc register and the isprx registers which give the interrupt software priority level of each interrupt vector (see table 5). the process- ing flow is shown in figure 14 when an interrupt request has to be serviced: normal processing is suspended at the end of the current instruction execution. the pc, x, a and cc registers are saved onto the stack. i1 and i0 bits of cc register are set according to the corresponding values in the isprx registers of the serviced interrupt vector. the pc is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to ainterrupt mappingo table for vector addresses). the interrupt service routine should end with the iret instruction which causes the contents of the saved registers to be recovered from the stack. note : as a consequence of the iret instruction, the i1 and i0 bits will be restored from the stack and the program in the previous level will resume. table 5. interrupt software priority levels figure 14. interrupt processing flowchart interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable) 1 1 aireto restore pc, x, a, cc stack pc, x, a, cc load i1:0 from interrupt sw reg. fetch next reset tli pendin g instruc tion i1:0 from stac k load pc from interrupt vector y n y n y n interrupt has the same or a lower software priority the inte rrupt stays pending than current one interrupt has a higher software priority than current one execute instructi on interrupt
st72311r, st72511r, st72512r, st72532r 29/164 interrupts (cont'd) servicing pending interrupts as several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: the highest software priority interrupt is serviced, if several interrupts have the same software pri- ority then the interrupt with the highest hardware priority is serviced first. figure 15 describes this decision process. figure 15. priority decision process when an interrupt request is not serviced immedi- ately, it is latched and then processed when its software priority combined with the hardware pri- ority becomes the highest one. note 1 : the hardware priority is exclusive while the software one is not. this allows the previous process to succeed with only one interrupt. note 2 : reset, trap and tli are non maskable and they can be considered as having the highest software priority in the decision process. different interrupt vector sources two interrupt source types are managed by the st7 interrupt controller: the non-maskable type (reset, tli, trap) and the maskable type (ex- ternal or from internal peripherals). non-maskable sources these sources are processed regardless of the state of the i1 and i0 bits of the cc register (see figure 14). after stacking the pc, x, a and cc registers (except for reset), the corresponding vector is loaded in the pc register and the i1 and i0 bits of the cc are set to disable interrupts (level 3). these sources allow the processor to exit halt mode. n tli (top level hardware interrupt) this hardware interrupt occurs when a specific edge is detected on the dedicated tli pin. its de- tailed specification is given in the miscellaneous register chapter. n trap (non maskable software interrupt) this software interrupt is serviced when the trap instruction is executed. it will be serviced accord- ing to the flowchart on figure 14 as a tli. n reset the reset source has the highest priority in the st7. this means that the first current routine has the highest software priority (level 3) and the high- est hardware priority. see the reset chapter for more details. maskable sources maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled and if its own interrupt software priority (in isprx registers) is higher than the one currently being serviced (i1 and i0 in cc register). if any of these two condi- tions is false, the interrupt is latched and thus re- mains pending. n external interrupts external interrupts allow the processor to exit from halt low power mode. external interrupt sensitivity is software selectable through the miscellaneous registers (miscrx). external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. if several input pins of a group connected to the same interrupt line are selected simultaneously, these will be logically ored. n peripheral interrupts usually the peripheral interrupts cause the mcu to exit from halt mode except those mentioned in the ainterrupt mappingo table. a peripheral interrupt occurs when a specific flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. the general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. note : the clearing sequence resets the internal latch. a pending interrupt (i.e. waiting for being serviced) will therefore be lost if the clear se- quence is executed. pending software different inte rrupts same highes t hardware priority serviced priority highest softwar e priority servic ed
st72311r, st72511r, st72512r, st72532r 30/164 interrupts (cont'd) 6.3 interrupts and low power modes all interrupts allow the processor to exit the wait low power mode. on the contrary, only external and other specified interrupts allow the processor to exit the halt modes (see column aexit from halto in ainterrupt mappingo table). when several pending interrupts are present while exiting halt mode, the first one serviced can only be an inter- rupt with exit from halt mode capability and it is selected through the same decision process shown in figure 15 note : if an interrupt, that is not able to exit from halt mode, is pending with the highest priority when exiting halt mode, this interrupt is serviced after the first one serviced. 6.4 concurrent & nested management the following figure 16 and figure 17 show two different interrupt management modes. the first is called concurrent mode and does not allow an in- terrupt to be interrupted, unlike the nested mode in figure 17 the interrupt hardware priority is given in this order from the lowest to the highest: main, it4, it3, it2, it1, it0, tli. the software priority is given for each interrupt. warning : a stack overflow may occur without no- tifying the software of the failure. figure 16. concurrent interrupt management figure 17. nested interrupt management main it4 it2 it1 tli it1 main it0 i1 hardware priority software 3 3 3 3 3 3/0 3 11 11 11 11 11 11 / 10 11 rim it2 it1 it4 tli it3 it0 it3 i0 10 priority level used stack = 10 bytes main it2 tli main it0 it2 it1 it4 tli it3 it0 hardware priority 3 2 1 3 3 3/0 3 11 00 01 11 11 11 rim it1 it4 it4 it1 it2 it3 i1 i0 11 / 10 10 software priority level used stack = 20 bytes
st72311r, st72511r, st72512r, st72532r 31/164 interrupts (cont'd) 6.5 interrupt register description cpu cc register interrupt bits read/write reset value: 111x 1010 (xah) bit 5, 3 = i1, i0 software interrupt priority these two bits indicate the current interrupt soft- ware priority. these two bits are set/cleared by hardware when entering in interrupt. the loaded value is given by the corresponding bits in the interrupt software pri- ority registers (isprx). they can be also set/cleared by software with the rim, sim, halt, wfi, iret and push/pop in- structions (see ainterrupt dedicated instruction seto table). *note : tli, trap and reset events are non maskable sources and can interrupt a level 3 pro- gram. interrupt software priority regis- ters (isprx) read/write (bit 7:4 of ispr3 are read only) reset values: 1111 1111 (ffh) these four registers contain the interrupt software priority of each interrupt vector. each interrupt vector (except reset and trap) has corresponding bits in these registers where its own software priority is stored. this corre- spondance is shown in the following table. each i1_x and i0_x bit value in the isprx regis- ters has the same meaning as the i1 and i0 bits in the cc register. level 0 can not be written (i1_x=1, i0_x=0). in this case, the previously stored value is kept. (ex- ample: previous=cfh, write=64h, result=44h) the reset, trap and tli vectors have no soft- ware priorities. when one is serviced, the i1 and i0 bits of the cc register are both set. *note : bits in the isprx registers which corre- spond to the tli can be read and written but they are not significant in the interrupt process man- agement. caution : if the i1_x and i0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: if the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. otherwise, the software priority stays unchanged up to the next interrupt request (after the iret of the inter- rupt x). 70 11 i1 h i0 nzc interrupt software priority level i1 i0 level 0 (main) low high 10 level 1 0 1 level 2 0 0 level 3 (= interrupt disable*) 1 1 70 ispr0 i1_3 i0_3 i1_2 i0_2 i1_1 i0_1 i1_0 i0_0 ispr1 i1_7 i0_7 i1_6 i0_6 i1_5 i0_5 i1_4 i0_4 ispr2 i1_11 i0_11 i1_10 i0_10 i1_9 i0_9 i1_8 i0_8 ispr3 1 1 1 1 i1_13 i0_13 i1_12 i0_12 vector address isprx bits fffbh-fffah i1_0 and i0_0 bits* fff9h-ff f8h i1_1 and i0_1 bits ... ... ffe1h-ffe0h i1_13 and i0_13 bits
st72311r, st72511r, st72512r, st72532r 32/164 interrupts (cont'd) table 6. dedicated interrupt instruction set note: during the execution of an interrupt routine, the halt, popcc, rim, sim and wfi instructions change the current software priority up to the next iret instruction or one of the previously mentioned instructions. in order not to lose the current software priority level, the rim, sim, halt, wfi and pop cc instructions should never be used in an interrupt routine. table 7. interrupt mapping instruction new description function/example i1 h i0 n z c halt entering halt mode 1 0 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c jrm jump if i1:0=11 i1:0=11 ? jrnm jump if i1:0<>11 i1:0<>11 ? pop cc pop cc from the stack mem => cc i1 h i0 n z c rim enable interrupt (level 0 set) load 10 in i1:0 of cc 1 0 sim disable interrupt (level 3 set) load 11 in i1:0 of cc 1 1 trap software trap software nmi 1 1 wfi wait for interrupt 1 0 n source block description register label priority order exit from halt address vector reset reset n/a highest priority lowest priority yes fffeh-ffffh trap software interrupt no fffch-fffdh 0 tli external top level interrupt miscr2 yes fffah-fffbh 1 mcc/rtc main clock controller time base interrupt mccsr fff8h-fff9h 2 ei0 external interrupt port a3..0 n/a fff6h-fff7h 3 ei1 external interrupt port f2..0 fff4h-fff5h 4 ei2 external interrupt port b3..0 fff2h-fff3h 5 ei3 external interrupt port b7..4 fff0h-fff1h 6 can can peripheral interrupts canisr ffeeh-ffe fh 7 spi spi peripheral interrupts spisr no ffech-ffedh 8 timer a timer a peripheral interrupts tasr ffeah-ffebh 9 timer b timer b peripheral interrupts tbsr ffe8h-ffe9h 10 sci sci peripheral interrupts scisr ffe6h-ffe7h 11 eeprom eeprom interrupt eecsr ffe4h-ffe5h 12 not used ffe2h-ffe3h 13 pwm art pwm art overflow interrupt artcsr yes ffe0h-ffe1h
st72311r, st72511r, st72512r, st72532r 33/164 interrupts (cont'd) table 8. nested interrupts register map and reset values address (hex.) register label 76543210 0024h ispr0 reset value ei1 ei0 mcc/rtc tli i1_3 1 i0_3 1 i1_2 1 i0_2 1 i1_1 1 i0_1 111 0025h ispr1 reset value spi can ei3 ei2 i1_7 1 i0_7 1 i1_6 1 i0_6 1 i1_5 1 i0_5 1 i1_4 1 i0_4 1 0026h ispr2 reset value eeprom sci timer b timer a i1_11 1 i0_11 1 i1_10 1 i0_10 1 i1_9 1 i0_9 1 i1_8 1 i0_8 1 0027h ispr3 reset value 1 1 1 1 pwmart not used i1_13 1 i0_13 1 i1_12 1 i0_12 1
st72311r, st72511r, st72512r, st72532r 34/164 7 power saving modes 7.1 introduction to give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the st7 (see figure 18): slow, wait (slow wait), ac- tive halt and halt. after a reset the normal operating mode is se- lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f cpu ). from run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific st7 software instruction whose action depends on the the oscil- lator status. figure 18. power saving mode transitions 7.2 slow mode this mode has two targets: to reduce power consumption by decreasing the internal clock in the device, to adapt the internal clock frequency (f cpu )to the available supply voltage. slow mode is controlled by three bits in the miscr1 register: the sms bit which enables or disables slow mode and two cpx bits which select the internal slow frequency (f cpu ). in this mode, the oscillator frequency can be divid- ed by 4, 8, 16 or 32 instead of 2 in normal operat- ing mode. the cpu and peripherals are clocked at this lower frequency. note : slow-wait mode is activated when enter- ring the wait mode while the device is already in slow mode. figure 19. slow mode clock transitions power consumption wait slow run active halt high low slow wait halt 00 01 sms cp1:0 f cpu new slow normal run mode miscr1 frequ ency request request f osc /2 f osc /4 f osc /8 f osc /2
st72311r, st72511r, st72512r, st72532r 35/164 power saving modes (cont'd) 7.3 wait mode wait mode places the mcu in a low power con- sumption mode by stopping the cpu. this power saving mode is selected by calling the `wfi' instruction. all peripherals remain active. during wait mode, the i[1:0] bits of the cc register are forced to `10', to enable all interrupts. all other registers and memory remain unchanged. the mcu remains in wait mode until an interrupt or reset occurs, whereupon the program counter branches to the starting address of the interrupt or reset service routine. the mcu will remain in wait mode until a reset or an interrupt occurs, causing it to wake up. refer to figure 20. figure 20. wait mode flow-chart note: 1. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. wfi instruction reset interrupt y n n y cpu oscillator peripherals i[1:0] bits on on 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off 10 on cpu oscillator peripherals i[1:0] bits on on xx 1) on 4096 cpu clock cycle delay
st72311r, st72511r, st72512r, st72532r 36/164 power saving modes (cont'd) 7.4 active-halt and halt modes active-halt and halt modes are the two low- est power consumption modes of the mcu. they are both entered by executing the `halt' instruc- tion. the decision to enter either in active-halt or halt mode is given by the mcc/rtc interrupt enable flag (oie bit in mccsr register). 7.4.1 active-halt mode active-halt mode is the lowest power con- sumption mode of the mcu with a real time clock available. it is entered by executing the `halt' in- struction when the oie bit of the main clock con- troller status register (mccsr) is set (see section 10.2 on page 52 for more details on the mccsr register). the mcu can exit active-halt mode on recep- tion of either an mcc/rtc interrupt, a specific in- terrupt (see table 7, ainterrupt mapping,o on page 32) or a reset. when exiting active- halt mode by means of a reset or an interrupt, a 4096 cpu cycle delay occurs. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 22). when entering active-halt mode, the i[1:0] bits in the cc register are forced to `10' to enable inter- rupts. therefore, if an interrupt is pending, the mcu wakes up immediately. in active-halt mode, only the main oscillator and its associated counter (mcc/rtc) are run- ning to keep a wake-up time base. all other periph- erals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). the safeguard against staying locked in active- halt mode is provided by the oscillator interrupt. note: as soon as the interrupt capability of one of the oscillators is selected (mccsr.oie bit set), entering active-halt mode while the watchdog is active does not generate a reset. this means that the device cannot spend more than a defined delay in this power saving mode. figure 21. active-halt timing overview figure 22. active-halt mode flow-chart notes: 1. peripheral clocked with an external clock source can still be active. 2. only the mcc/rtc interrupt and some specific interrupts can exit the mcu from active-halt mode (such as external interrupt). refer to table 7, ainterrupt mapping,o on page 32 for more details. 3. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and restored when the cc register is popped. mccsr oie bit power saving mode entered when halt instruction is executed 0 halt mode 1 active-halt mode halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector active [mccsr.oie=1] halt instruction reset interrupt 2) y n n y cpu oscillator peripherals 1) i[1:0] bits on off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 3) on cpu oscillator peripherals i[1:0] bits on on xx 3) on 4096 cpu clock cycle delay (mccsr.oie=1)
st72311r, st72511r, st72512r, st72532r 37/164 power saving modes (cont'd) 7.4.2 halt mode the halt mode is the lowest power consumption mode of the mcu. it is entered by executing the `halt' instruction when the oie bit of the main clock controller status register (mccsr) is cleared (see section 10.2 on page 52 for more de- tails on the mccsr register). the mcu can exit halt mode on reception of ei- ther a specific interrupt (see table 7, ainterrupt mapping,o on page 32) or a reset. when exiting halt mode by means of a reset or an interrupt, the oscillator is immediately turned on and the 4096 cpu cycle delay is used to stabilize the os- cillator. after the start up delay, the cpu resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see figure 24). when entering halt mode, the i bit in the cc reg- ister is forced to 0 to enable interrupts. therefore, if an interrupt is pending, the mcu wakes immedi- ately. in halt mode, the main oscillator is turned off causing all internal processing to be stopped, in- cluding the operation of the on-chip peripherals. all peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscilla- tor). the compatibility of watchdog operation with halt mode is configured by the awdghalto op- tion bit of the option byte. the halt instruction when executed while the watchdog system is en- abled, can generate a watchdog reset (see section 14.1 on page 158 for more details). figure 23. halt timing overview figure 24. halt mode flow-chart notes: 1. wdghalt is an option bit. see option byte sec- tion for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu from halt mode (such as external interrupt). re- fer to table 7, ainterrupt mapping,o on page 32 for more details. 4. before servicing an interrupt, the cc register is pushed on the stack. the i[1:0] bits of the cc reg- ister are set to the current software priority level of the interrupt routine and recovered when the cc register is popped. halt run run 4096 cpu cycle delay reset or interrupt halt instruction fetch vector [mccsr.oie=0] halt instruction reset interrupt 3) y n n y cpu oscillator peripherals 2) i[1:0] bits off off 10 off fetch reset vector or service interrupt cpu oscillator peripherals i[1:0] bits on off xx 4) on cpu oscillator peripherals i[1:0] bits on on xx 4) on 4096 cpu clock cycle delay watchdog enable disable wdghalt 1) 0 watchdog reset 1 (mccsr.oie=0)
st72311r, st72511r, st72512r, st72532r 38/164 8 i/o ports 8.1 introduction the i/o ports offer different functional modes: transfer of data through digital inputs and outputs and for specific pins: external interrupt generation alternate signal input/output for the on-chip pe- ripherals. an i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without interrupt generation) or digital output. 8.2 functional description each port has 2 main registers: data register (dr) data direction register (ddr) and one optional register: option register (or) each i/o pin may be programmed using the corre- sponding register bits in the ddr and or regis- ters: bit x corresponding to pin x of the port. the same correspondence is used for the dr register. the following description takes into account the or register, (for specific ports which do not pro- vide this register refer to the i/o port implementa- tion section). the generic i/o block diagram is shown in figure 25 8.2.1 input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the or register. notes : 1. writing the dr register modifies the latch value but does not affect the pin status. 2. when switching from input to output mode, the dr register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. external interrupt function when an i/o is configured as input with interrupt, an event on this i/o can generate an external inter- rupt request to the cpu. each pin can independently generate an interrupt request. the interrupt sensitivity is independently programmable using the sensitivity bits in the mis- cellaneous register. each external interrupt vector is linked to a dedi- cated group of i/o port pins (see pinout description and interrupt section). if several input pins are se- lected simultaneously as interrupt source, these are logically anded. for this reason if one of the interrupt pins is tied low, it masks the other ones. in case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see figure 26). the external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. to clear an unwanted pending interrupt by software, the sensitivity bits in the miscellane- ous register must be modified. 8.2.2 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ- ing the dr register applies this digital value to the i/o pin through the latch. then reading the dr reg- ister returns the previously stored value. two different output modes can be selected by software through the or register: output push-pull and open-drain. dr register value and output pin status: 8.2.3 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. this alternate function takes priority over the standard i/o programming. when the signal is coming from an on-chip periph- eral, the i/o pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). when the signal is going to an on-chip peripheral, the i/o pin must be configured in input mode. in this case, the pin state is also digitally readable by addressing the dr register. note : input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. when an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. dr push-pu ll open-drain 0v ss vss 1v dd floating
st72311r, st72511r, st72512r, st72532r 39/164 i/o ports (cont'd) figure 25. i/o port general block diagram table 9. i/o port mode options legend : ni - not implemented off - implemented not activated on - implemented and activated note : the diode to v dd is not implemented in the true open drain pads. a local protection between the pad and v ss is implemented to protect the de- vice against positive stress. configuration mode pull-up p-buffer diodes to v dd to v ss input floating with/without interrupt off off on on pull-up with/without interrupt on output push-pull off on open drain (logic level) off true open drain ni ni ni (see note) dr ddr or data bus pad v dd alternate enable alternate output 1 0 or sel ddr sel dr sel pull-up condition p-buffer (see table below) n-buffer pull-up (see table below) 1 0 analog input if implemented alternate input v dd diodes (see table below) from other bits external source (ei x ) interrupt polarity selection cmos schmitt trigger register access
st72311r, st72511r, st72512r, st72532r 40/164 i/o ports (cont'd) table 10. i/o port configurations notes: 1. when the i/o port is in input configuration and the associated alternate function is enabled as an output, reading the dr register will read the alternate function output status. 2. when the i/o port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the dr register content. hardware configu ration input 1) open-drain output 2) push-pull output 2) condition pad v dd r pu external interru pt polarity data bus pull-up interrupt dr register access w r from other pins source (ei x ) selection dr register conditio n alternate input not implemented in true open drain i/o ports analog input pad r pu data b us dr dr regist er access r/w v dd alternate alternate enable output regist er not implemented in true open drain i/o ports pad r pu data b us dr dr regist er access r/w v dd alternate alternate enable output regist er not implemented in true open drain i/o ports
st72311r, st72511r, st72512r, st72532r 41/164 i/o ports (cont'd) caution : the alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. analog alternate function when the pin is used as an adc input, the i/o must be configured as floating input. the analog multiplexer (controlled by the adc registers) switches the analog voltage present on the select- ed pin to the common analog rail which is connect- ed to the adc input. it is recommended not to change the voltage level or loading on any port pin while conversion is in progress. furthermore it is recommended not to have clocking pins located close to a selected an- alog pin. warning : the analog input voltage level must be within the limits stated in the absolute maxi- mum ratings. 8.3 i/o port implementation the hardware implementation on each i/o port de- pends on the settings in the ddr and or registers and specific feature of the i/o port such as adc in- put or true open drain. switching these i/o ports from one state to anoth- er should be done in a sequence that prevents un- wanted side effects. recommended safe transi- tions are illustrated in figure 26 other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. figure 26. interrupt i/o port state transitions the i/o port register configurations are summa- rized as follows. standard ports pa5:4, pc7:0, pd7:0, pe7:3, pe1:0, pf7:3 interrupt ports pa2:0, pb7:5, pb2:0, pf1:0 (with pull-up) pa3, pb4, pb3, pf2 (without pull-up) true open drain ports pa7:6 pull-up input port (cantx requirement) pe2 01 floating/pull-up interrupt input 00 floating (reset state) input 10 open-drain output 11 push-pull output xx = ddr, or mode ddr or floating input 0 0 pull-up input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 pull-up interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr or floating input 0 0 floating interrupt input 0 1 open drain output 1 0 push-pull output 1 1 mode ddr floating input 0 open drain (high sink ports) 1 mode pull-up input
st72311r, st72511r, st72512r, st72532r 42/164 i/o ports (cont'd) 8.4 low power modes 8.5 interrupts the external interrupt event generates an interrupt if the corresponding configuration is selected with ddr and or registers and the interrupt mask in the cc register is not active (rim instruction). table 11. port configuration * note: when the cantx alternate function is selected the io port operates in output push-pull mode. mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. halt no effect on i/o ports. external interrupts cause the device to exit from halt mode. interrupt event event flag enable control bit exit from wait exit from halt external interrupt on selected external event - ddrx orx yes yes port pin name input outpu t or = 0 or = 1 or = 0 or = 1 high-sink port a pa7:6 floating true open-drain yes pa5:4 floating pull-up open drain push-pull pa3 floating floating interrupt open drain push-pull no pa2:0 floating pull-up interrupt open drain push-pull port b pb4, pb3 floating floating interrupt open drain push-pull pb7:5, pb2:0 floating pull-up interrupt open drain push-pull port c pc7:0 floating pull-up open drain push-pull pc3:2 only port d pd7:0 floating pull-up open drain push-pull no port e pe7:3, pe1:0 floating pull-up open drain push-pull pe7:4 only pe2 pull-up input only * no port f pf7:3 floating pull-up open drain push-pull pf7:6 only pf2 floating floating interrupt open drain push-pull no pf1:0 floating pull-up interrupt open drain push-pull
st72311r, st72511r, st72512r, st72532r 43/164 i/o ports (cont'd) 8.5.1 register description data register (dr) port x data register pxdr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register 8 bits. the dr register has a specific behaviour accord- ing to the selected input/output configuration. writ- ing the dr register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. reading the dr register returns either the dr register latch content (pin configured as output) or the digital value applied to the i/o pin (pin configured as input). data direction register (ddr) port x data direction register pxddr with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register 8 bits. the ddr register gives the input/output direction configuration of the pins. each bits is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register pxor with x = a, b, c, d, e or f. read/write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register 8 bits. for specific i/o pins, this register is not implement- ed. in this case the ddr register is enough to se- lect the i/o pin configuration. the or register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. each bit is set and cleared by software. input mode: 0: floating input 1: pull-up input with or without interrupt output mode: 0: output open drain (with p-buffer unactivated) 1: output push-pull 70 d7 d6 d5 d4 d3 d2 d1 d0 70 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 70 o7 o6 o5 o4 o3 o2 o1 o0
st72311r, st72511r, st72512r, st72532r 44/164 i/o ports (cont'd) table 12. i/o port register map and reset values address (hex.) register label 76543210 reset value of all io port registers 00000000 0000h padr msb lsb 0001h paddr 0002h paor 0004h pcdr msb lsb 0005h pcddr 0006h pcor 0008h pbdr msb lsb 0009h pbddr 000ah pbor 000ch pedr msb lsb 000dh peddr 000eh peor 0010h pddr msb lsb 0011h pdddr 0012h pdor 0014h pfdr msb lsb 0015h pfddr 0016h pfor
st72311r, st72511r, st72512r, st72532r 45/164 9 miscellaneous registers the miscellaneous registers allow control over several features such as the external interrupts or the i/oalternate functions. 9.1 i/o port interrupt sensitivity the external interrupt sensitivity is controlled by the ipa, ipb and isxx bits of the miscellaneous registers (figure 27). this control allows to have up to 4 fully independent external interrupt source sensitivities. each external interrupt source can be generated on four (or five) different events on the pin: n falling edge n rising edge n falling and rising edge n falling edge and low level n rising edge and high level (only for ei0 and ei2) to guarantee correct functionality, the sensitivity bits in the miscr registers must be modified only when the i1 and i0 bits of the cc register are both set to 1 (level 3). see i/o port register and miscel- laneous register descriptions for more details on the programming. 9.2 i/o port alternate functions the miscr registers allow to manage four i/o port miscellaneous alternate functions: n main clock signal (f osc /2) output on pf0 n a beep signal output on pf1 (with three selectable audio frequencies) n a tli management on a dedicated pin n a spi ss pin internal control to use the pc7 i/o port function while the spi is active. these functions are described in details in the section 9.3 omiscellaneous registerso on page 46. figure 27. external interrupt sources vs miscr ei0 inter rupt source ei1 interrupt source is20 is21 miscr1 sensi tivity control pa3 pa2 miscr2.ipa pa1 pa0 pf2 pf1 pf0 ei2 interrupt source ei3 interrupt source is10 is11 miscr1 sensi tivity control pb3 pb2 miscr2.ipb pb1 pb0 pb7 pb6 pb5 pb4 sources sources sources sources
st72311r, st72511r, st72512r, st72532r 46/164 miscellaneous registers (cont'd) 9.3 miscellaneous registers miscellaneous register 1 (miscr1) read/write reset value: 0000 0000 (00h) bit 7:6 = is1[1:0] ei2 and ei3 sensitivity the interrupt sensitivity, defined using the is1[1:0] bits, is applied to the following external interrupts: - ei2 (port b3..0) - ei3 (port b7..4) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 5 = mco main clock out selection this bit enables the mco alternate function on the pf0 i/o port. it is set and cleared by software. 0: mco alternate function disabled (i/o pin free for general-purpose i/o) 1: mco alternate function enabled (f osc /2on i/o port) note : to reduce power consumption, the mco function is not active in active-halt mode. bit 4:3 = is2[1:0] ei0 and ei1 sensitivity the interrupt sensitivity, defined using the is2[1:0] bits, is applied to the following external interrupts: - ei0 (port a3..0) - ei1 (port f2..0) these 2 bits can be written only when i1 and i0 of the cc register are both set to 1 (level 3). bit 2:1 = cp[1:0] cpu clock prescaler these bits select the cpu clock prescaler which is applied in the different slow modes. their action is conditioned by the setting of the sms bit. these two bits are set and cleared by software bit 0 = sms slow mode select this bit is set and cleared by software. 0: normal mode. f cpu = f osc /2 1: slow mode. f cpu is given by cp1, cp0 see section 7.2 oslow modeo on page 34 and section 10.2 omain clock controller with real time clock timer (mcc/rtc)o on page 52 for more details. 70 is11 is10 mco is21 is20 cp1 cp0 sms is11 is10 external interrupt sensitivity miscr2.ipb=0 miscr2.ipb=1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is11 is10 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity miscr2.ipa=0 miscr2.ipa=1 00 falling edge & low level rising edge & high level 0 1 rising edge only falling edge only 1 0 falling edge only rising edge only 1 1 rising and falling edge is21 is20 external interrupt sensitivity 0 0 falling edge & low level 0 1 rising edge only 1 0 falling edge only 1 1 rising and falling edge f cpu in slow mode cp1 cp0 f osc /4 0 0 f osc /8 1 0 f osc /16 0 1 f osc /32 1 1
st72311r, st72511r, st72512r, st72532r 47/164 miscellaneous registers (cont'd) miscellaneous register 2 (miscr2) read/write reset value: 0000 0000 (00h) bit 7 = ipa interrupt polarity for port a this bit is used to invert the sensitivity of the port a [3:0] external interrupts. it is set and cleared by software. 0: no sensitivity inversion 1: sensitivity inversion see section 9.1 oi/o port interrupt sensi- tivityo on page 45 and the description of the is2x bits of the miscr1 register for more details. bit 6 = ipb interrupt polarity for port b this bit is used to invert the sensitivity of the port b [3:0] external interrupts. it is set and cleared by software. 0: no sensitivity inversion 1: sensitivity inversion see section 9.1 oi/o port interrupt sensi- tivityo on page 45 and the description of the is1x bits of the miscr1 register for more details. bit 5:4 = bc[1:0] beep control these 2 bits select the pf1 pin beep capability. the beep output signal is available in active- halt mode but has to be disabled to reduce the consumption. bit 3 = tlis tli sensitivity this bit allows to toggle the tli edge sensitivity. it can be set and cleared by software only when tlie bit is cleared. 0: falling edge 1: rising edge bit 2 = tlie tli enable this bit allows to enable or disable the tli capabil- ity on the dedicated pin. it is set and cleared by software. 0: tli disabled 1: tli enabled note : a parasitic interrupt can be generated when clearing the tlie bit. bit 1 = ssm ss mode selection this bit is set and cleared by software. 0: normal mode - the level of the spi ss signal is input from the external ss pin. 1: i/o mode (pc7), the level of the spi ss signal is read from the ssi bit. bit 0 = ssi ss internal mode this bit replaces pin ss of the spi when bit ssm is set to 1. (see spi description). it is set and cleared by software. 70 ipa ipb bc1 bc0 tlis tlie ssm ssi bc1 bc0 beep mode with f osc =16mhz 0 0 off 0 1 ~2-khz output beep signal ~50% duty cycle 1 0 ~1-khz 1 1 ~500-hz
st72311r, st72511r, st72512r, st72532r 48/164 miscellaneous registers (cont'd) table 13. miscellaneous register map and reset values address (hex.) register label 76543210 0020h miscr1 reset value is11 0 is10 0 mco 0 is21 0 is20 0 cp1 0 cp0 0 sms 0 0040h miscr2 reset value ipa 0 ipb 0 bc1 0 bc0 0 tlis 0 tlie 0 ssm 0 ssi 0
st72311r, st72511r, st72512r, st72532r 49/164 10 on-chip peripherals 10.1 watchdog timer (wdg) 10.1.1 introduction the watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. the watchdog cir- cuit generates an mcu reset on expiry of a pro- grammed time period, unless the program refresh- es the counter's contents before the t6 bit be- comes cleared. 10.1.2 main features n programmable timer (64 increments of 12288 cpu cycles) n programmable reset n reset (if watchdog activated) after a halt instruction or when the t6 bit reaches zero n hardware watchdog selectable by option byte n watchdog reset indicated by status flag (in versions with safe reset option only) 10.1.3 functional description the counter value stored in the cr register (bits t[6:0]), is decremented every 12,288 machine cy- cles, and the length of the timeout period can be programmed by the user in 64 increments. if the watchdog is activated (the wdga bit is set) and when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 500ns. figure 28. watchdog block diagram reset wdga 7-bit downcounter f cpu t6 t0 clock divider watchdog control register (cr) 12288 t1 t2 t3 t4 t5
st72311r, st72511r, st72512r, st72532r 50/164 watchdog timer (cont'd) the application program must write in the cr reg- ister at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see table 14 .watchdog timing (fcpu = 8 mhz)): the wdga bit is set (watchdog enabled) the t6 bit is set to prevent generating an imme- diate reset the t[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. table 14.watchdog timing (f cpu = 8 mhz) notes: following a reset, the watchdog is disa- bled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re- set (the wdga bit is set and the t6 bit is cleared). if the watchdog is activated, the halt instruction will generate a reset. 10.1.4 hardware watchdog option if hardware watchdog is selected by option byte, the watchdog is always active and the wdga bit in the cr is not used. refer to the device-specific option byte descrip- tion. 10.1.5 low power modes 10.1.6 interrupts none. 10.1.7 register description control register (cr) read/write reset value: 0111 1111 (7fh) bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled note: this bit is not used if the hardware watch- dog option is enabled by option byte. bit 6:0 = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a reset is produced when it rolls over from 40h to 3fh (t6 becomes cleared). status register (sr) read/write reset value*: 0000 0000 (00h) bit 0 = wdogf watchdog flag . this bit is set by a watchdog reset and cleared by software or a power on/off reset. this bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: no watchdog reset occurred 1: watchdog reset occurred * only by software and power on/off reset note: this register is not used in versions without lvd reset. cr register initial value wdg timeout period (ms) max ffh 98.304 min c0h 1.536 mode description wait no effect on watchdog. halt immediate reset generation as soon as the halt instruction is executed if the watchdog is activated (wdga bit is set). 70 wdga t6 t5 t4 t3 t2 t1 t0 70 - - - - - - - wdogf
st72311r, st72511r, st72512r, st72532r 51/164 watchdog timer (cond't) table 15. watchdog timer register map and reset values address (hex.) register label 76543210 002ah wdgcr reset value wdga 0 t6 1 t5 1 t4 1 t3 1 t2 1 t1 1 t0 1 002bh wdgsr reset value - 0 - 0 - 0 - 0 - 0 - 0 - 0 wdogf 0
st72311r, st72511r, st72512r, st72532r 52/164 10.2 main clock controller with real time clock timer (mcc/rtc) the main clock controller consists of three differ- ent functions: n a programmable cpu clock prescaler n a clock-out signal to supply external devices n a real time clock timer with interrupt capability each function can be used independently and si- multaneously. 10.2.1 programmable cpu clock prescaler the programmable cpu clock prescaler supplies the clock for the st7 cpu and its internal periph- erals. it manages slow power saving mode (see section 7.2 oslow modeo on page 34 for more details). the prescaler selects the f cpu main clock frequen- cy and is controlled by three bits in the miscr1 register: cp[1:0] and sms. caution : the prescaler does not act on the can peripheral clock source. this peripheral is always supplied by the f osc /2 clock source. 10.2.2 clock-out capability the clock-out capability is an alternate function of an i/o port pin that outputs a f osc /2 clock to drive external devices. it is controlled by the mco bit in the miscr1 register. caution : when selected, the clock out pin sus- pends the clock during active-halt mode. 10.2.3 real time clock timer (rtc) the counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. four different time bases depend- ing directly on f osc are available. the whole func- tionality is controlled by four bits of the mccsr register: tb[1:0], oie and oif. when the rtc interrupt is enabled (oie bit set), the st7 enters active-halt mode when the halt instruction is executed. see section 7.4 oactive-halt and halt modeso on page 36 for more details. figure 29. main clock controller (mcc/rtc) block diagram div2,4,8,16 mcc/rtc interrupt div 2 sms cp1 cp0 tb1 tb0 oie oif cpu clock miscr1 rtc counter clock to can to cpu and peripherals f osc f cpu mco port function alternate mco - - - - 0 0 0 0 mccsr f osc /2 peripheral
st72311r, st72511r, st72512r, st72532r 53/164 main clock controller with real time clock timer (cont'd) 10.2.4 register description miscellaneous register 1 (miscr1) see amiscellaneous registerso section. main clock control/status register (mccsr) read/write reset value: 0000 0001 (01h) bit 7:4 = reserved, always read as 0. bit 3:2 = tb[1:0] time base control these bits select the programmable divider time base. they are set and cleared by software. a modification of the time base is taken into ac- count at the end of the current period (previously set) to avoid an unwanted time shift. this allows to use this time base as a real time clock. bit 1 = oie oscillator interrupt enable this bit set and cleared by software. 0: oscillator interrupt disabled 1: oscillator interrupt enabled this interrupt can be used to exit from active- halt mode. when this bit is set, calling the st7 software halt instruction enters the active-halt power saving mode . bit 0 = oif oscillator interrupt flag this bit is set by hardware and cleared by software reading the csr register. it indicates when set that the main oscillator has reached the selected elapsed time (tb1:0). 0: timeout not reached 1: timeout reached caution : the bres and bset instructions must not be used on the mccsr register to avoid unintentionally clearing the oif bit. 10.2.5 low power modes 10.2.6 interrupts the mcc/rtc interrupt event generates an inter- rupt if the oie bit of the mccsr register is set and the interrupt mask in the cc register is not active (rim instruction). note : 1. the mcc/rtc interrupt allows to exit from ac- tive-halt mode, not from halt mode. table 16. mcc/rtc register map and reset values 70 0000tb1tb0oieoif counter prescaler time base tb1 tb0 f osc =8mhz f osc =16mhz 32000 4ms 2ms 0 0 64000 8ms 4ms 0 1 160000 20ms 10ms 1 0 400000 50ms 25ms 1 1 mode description wait no effect on mcc/rtc peripheral. mcc/rtc interrupt cause the device to exit from wait mode. active- halt no effect on mcc/rtc counter (oie bit is set), the registers are frozen. mcc/rtc interrupt cause the device to exit from active-halt mode. halt mcc/rtc counter and registers are frozen. mcc/rtc operation resumes when the mcu is woken up by an interrupt with aexit from halto capability. interrupt event event flag enable control bit exit from wait exit from halt time base overflow event oif oie yes no 1) address (hex.) register label 76543210 0029h mccsr reset value 0 0 0 0 tb1 0 tb0 0 oie 0 oif 1
st72311r, st72511r, st72512r, st72532r 54/164 10.3 pwm auto-reload timer (art) 10.3.1 introduction the pulse width modulated auto-reload timer on-chip peripheral consists of an 8-bit auto reload counter with compare capabilities and of a 7-bit prescaler clock source. these resources allow three possible operating modes: generation of up to 4 independent pwm signals output compare and time base interrupt external event detector the two first modes can be used together with a single counter frequency. the timer can be used to wake up the mcu from wait and halt modes. figure 30. pwm auto-reload timer block diagram ovf interrupt excl cc2 cc1 cc0 tce fcrl oie ovf artcsr f input pwmx port funct ion alternate ocrx compare regist er programmable prescaler 8-bit counter (car registe r) arr register load opx polarity control oex pwmcr mux f cpu dcrx register load f counter artclk f ext
st72311r, st72511r, st72512r, st72532r 55/164 pwm auto-reload timer (cont'd) 10.3.2 functional description counter the free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal. it is possible to read or write the contents of the counter on the fly by reading or writing the counter access register (car). when a counter overflow occurs, the counter is automatically reloaded with the contents of the arr register (the prescaler is not affected). counter clock and prescaler the counter clock frequency is given by: f counter =f input /2 cc[2:0] the timer counter's input clock (f input ) feeds the 7-bit programmable prescaler, which selects one of the 8 available taps of the prescaler, as defined by cc[2:0] bits in the control/status register (csr). thus the division factor of the prescaler can be set to 2 n (where n = 0, 1,..7). this f input frequency source is selected through the excl bit of the csr register and can be either the f cpu or an external input frequency f ext . the clock input to the counter is enabled by the tce (timer counter enable) bit in the csr regis- ter. when tce is reset, the counter is stopped and the prescaler and counter contents are frozen. when tce is set, the counter runs at the rate of the selected clock source. counter and prescaler initialization after reset, the counter and the prescaler are cleared and f input =f cpu . the counter can be initialized by: writing to the arr register and then setting the fcrl (force counter re-load) and the tce (timer counter enable) bits in the csr register. writing to the car counter access register, in both cases the 7-bit prescaler is also cleared, whereupon counting will start from a known value. direct access to the prescaler is not possible. output compare control the timer compare function is based on four differ- ent comparisons with the counter (one for each pwmx output). each comparison is made be- tween the counter value and an output compare register (ocrx) value. this ocrx register can not be accessed directly, it is loaded from the duty cy- cle register (dcrx) at each overflow of the coun- ter. this double buffering method avoids glitch gener- ation when changing the duty cycle on the fly. figure 31. output compare control counter fdh feh ffh fdh feh ffh fdh feh arr=fdh f counter ocrx dcrx fdh feh fdh feh ffh pwmx
st72311r, st72511r, st72512r, st72532r 56/164 pwm auto-reload timer (cont'd) independent pwm signal generation this mode allows up to four pulse width modulat- ed signals to be generated on the pwmx output pins with minimum core processing overhead. this function is stopped during halt mode. each pwmx output signal can be selected inde- pendently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o pin is configured as out- put push-pull alternate function. the pwm signals all have the same frequency which is controlled by the counter period and the arr register value. f pwm =f counter / (256 - arr) when a counter overflow occurs, the pwmx pin level is changed depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the output compare register (ocrx) the corresponding pwmx pin level is restored. it should be noted that the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the ocrx register must be greater than the contents of the arr register. the maximum available resolution for the pwmx duty cycle is: resolution = 1 / (256 - arr) note : to get the maximum resolution (1/256), the arr register must be 0. with this maximum reso- lution, 0% and 100% can be obtained by changing the polarity. figure 32. pwm auto-reload timer function figure 33. pwm signal from 0% to 100% duty cycle duty cycle register auto-reload register pwmx output t 255 000 with oex=1 and opx=0 (arr) (dcrx) with oex=1 and opx=1 counter counter pwmx output t with oex=1 and opx=0 fdh feh ffh fdh feh ffh fdh feh ocrx=fch ocrx=fdh ocrx=feh ocrx=ffh arr=fdh f counter
st72311r, st72511r, st72512r, st72532r 57/164 pwm auto-reload timer (cont'd) output compare and time base interrupt on overflow, the ovf flag of the csr register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, oie, in the csr register, is set. the ovf flag must be reset by the user software. this interrupt can be used as a time base in the application. external clock and event detector mode using the f ext external prescaler input clock, the auto-reload timer can be used as an external clock event detector. in this mode, the arr register is used to select the n event number of events to be counted before setting the ovf flag. n event = 256 - arr when entering halt mode while f ext is selected, all the timer control registers are frozen but the counter continues to increment. if the oie bit is set, the next overflow of the counter will generate an interrupt which wakes up the mcu. figure 34. external event detector example (3 counts) counter t fdh feh ffh fdh ovf csr read interrupt arr=fdh f ext =f counter feh ffh fdh if oie=1 interrupt if oie=1 csr read
st72311r, st72511r, st72512r, st72532r 58/164 pwm auto-reload timer (cont'd) 10.3.3 register description control / status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = excl external clock this bit is set and cleared by software. it selects the input clock for the 7-bit prescaler. 0: cpu clock. 1: external clock. bit 6:4 = cc[2:0] counter clock control these bits are set and cleared by software. they determine the prescaler division ratio from f input . bit 3 = tce timer counter enable this bit is set and cleared by software. it puts the timer in the lowest power consumption mode. 0: counter stopped (prescaler and counter frozen). 1: counter running. bit 2 = fcrl force counter re-load this bit is write-only and any attempt to read it will yield a logical zero. when set, it causes the contents of arr register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. bit 1 = oie overflow interrupt enable this bit is set and cleared by software. it allows to enable/disable the interrupt which is generated when the ovf bit is set. 0: overflow interrupt disable. 1: overflow interrupt enable. bit 0 = ovf overflow flag this bit is set by hardware and cleared by software reading the csr register. it indicates the transition of the counter from ffh to the arr value . 0: new transition not yet reached 1: transition reached counter access register (car) read/write reset value: 0000 0000 (00h) bit 7:0 = ca[7:0] counter access data these bits can be set and cleared either by hard- ware or by software. the car register is used to read or write the auto-reload counter aon the flyo (while it is counting). auto-reload register (arr) read/write reset value: 0000 0000 (00h) bit 7:0 = ar[7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register has two pwm management func- tions: adjusting the pwm frequency setting the pwm duty cycle resolution pwm frequency vs. resolution: 70 excl cc2 cc1 cc0 tce fcrl oie ovf f counter with f input =8 mhz cc2 cc1 cc0 f input f input /2 f input /4 f input /8 f input /16 f input /32 f input /64 f input / 128 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 70 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 70 ar7 ar6 ar5 ar4 ar3 ar2 ar1 ar0 arr value resolution f pwm min max 0 8-bit ~0.244-khz 31.25-khz [ 0..127 ] > 7-bit ~0.244-khz 62.5-khz [ 128..191 ] > 6-bit ~0.488-khz 125-khz [ 192..223 ] > 5-bit ~0.977-khz 250-khz [ 224..239 ] > 4-bit ~1.953-khz 500-khz
st72311r, st72511r, st72512r, st72532r 59/164 pwm auto-reload timer (cont'd) pwm control register (pwmcr) read/write reset value: 0000 0000 (00h) bit 7:4 = oe[3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels inde- pendently acting on the corresponding i/o pin. 0: pwm output disabled. 1: pwm output enabled. bit 3:0 = op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the four pwm output signals. note : when an opx bit is modified, the pwmx out- put signal polarity is immediately reversed. duty cycle registers (dcrx) read/write reset value: 0000 0000 (00h) bit 7:0 = dc[7:0] duty cycle data these bits are set and cleared by software. a dcrx register is associated with the ocrx reg- ister of each pwm channel to determine the sec- ond edge location of the pwm signal (the first edge location is common to all channels and given by the arr register). these dcr registers allow the duty cycle to be set independently for each pwm channel. 70 oe3 oe2 oe1 oe0 op3 op2 op1 op0 pwmx output level opx counter <= ocrx counter > ocrx 100 011 70 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0
st72311r, st72511r, st72512r, st72532r 60/164 pwm auto-reload timer (cont'd) table 17. pwm auto-reload timer register map and reset values address (hex.) register label 76543210 0072h pwmdcr3 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0073h pwmdcr2 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0074h pwmdcr1 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0075h pwmdcr0 reset value dc7 0 dc6 0 dc5 0 dc4 0 dc3 0 dc2 0 dc1 0 dc0 0 0076h pwmcr reset value oe3 0 oe2 0 oe1 0 oe0 0 op3 0 op2 0 op1 0 op0 0 0077h artcsr reset value excl 0 cc2 0 cc1 0 cc0 0 tce 0 fcrl 0 oie 0 ovf 0 0078h artcar reset value ca7 0 ca6 0 ca5 0 ca4 0 ca3 0 ca2 0 ca1 0 ca0 0 0079h artarr reset value ar7 0 ar6 0 ar5 0 ar4 0 ar3 0 ar2 0 ar1 0 ar0 0
st72311r, st72511r, st72512r, st72532r 61/164 10.4 16-bit timer 10.4.1 introduction the timer consists of a 16-bit free-running counter driven by a programmable prescaler. it may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals ( input capture ) or generation of up to two out- put waveforms ( output compare and pwm ). pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the cpu clock prescaler. some st7 devices have two on-chip 16-bit timers. they are completely independent, and do not share any resources. they are synchronized after a mcu reset as long as the timer clock frequen- cies are not modified. this description covers one or two 16-bit timers. in st7 devices with two timers, register names are prefixed with ta (timer a) or tb (timer b). 10.4.2 main features n programmable prescaler: f cpu divided by 2, 4 or 8. n overflow status flag and maskable interrupt n external clock input (must be at least 4 times slower than the cpu clock speed) with the choice of active edge n output compare functions with 2 dedicated 16-bit registers 2 dedicated programmable signals 2 dedicated status flags 1 dedicated maskable interrupt n input capture functions with 2 dedicated 16-bit registers 2 dedicated active edge selection signals 2 dedicated status flags 1 dedicated maskable interrupt n pulse width modulation mode (pwm) n one pulse mode n 5 alternate functions on i/o ports (icap1, icap2, ocmp1, ocmp2, extclk)* the block diagram is shown in figure 35. *note: some timer pins may not available (not bonded) in some st7 devices. refer to the device pin out description. when reading an input signal on a non-bonded pin, the value will always be `1'. 10.4.3 functional description 10.4.3.1 counter the main block of the programmable timer is a 16-bit free running upcounter and its associated 16-bit registers. the 16-bit registers are made up of two 8-bit registers called high & low. counter register (cr): counter high register (chr) is the most sig- nificant byte (ms byte). counter low register (clr) is the least sig- nificant byte (ls byte). alternate counter register (acr) alternate counter high register (achr) is the most significant byte (ms byte). alternate counter low register (aclr) is the least significant byte (ls byte). these two read-only 16-bit registers contain the same value but with the difference that reading the aclr register does not clear the tof bit (timer overflow flag), located in the status register, (sr), (see note at the end of paragraph titled 16-bit read sequence). writing in the clr register or aclr register resets the free running counter to the fffch value. both counters have a reset value of fffch (this is the only value which is reloaded in the 16-bit tim- er). the reset value of both counters is also fffch in one pulse mode and pwm mode. the timer clock depends on the clock control bits of the cr2 register, as illustrated in table 18 clock control bits. the value in the counter register re- peats every 131.072, 262.144 or 524.288 cpu clock cycles depending on the cc[1:0] bits. the timer frequency can be f cpu /2, f cpu /4, f cpu /8 or an external frequency.
st72311r, st72511r, st72512r, st72532r 62/164 16-bit timer (cont'd) figure 35. timer block diagram mcu-peripheral interface counter alternate output compare register output compare edge detect overflow detect circuit 1/2 1/4 1/8 8-bit buffer st7 internal bus latch1 ocmp1 icap1 extclk f cpu timer interrupt icf2 icf1 0 0 0 ocf2 ocf1 tof pwm oc1e exedg iedg2 cc0 cc1 oc2e opm folv2 icie olvl1 iedg1 olvl2 folv1 ocie toie icap2 latch2 ocmp2 8 8 8 low 16 8high 16 16 16 16 (control register 1) cr1 (control register 2) cr2 (status register) sr 6 16 888 8 88 high low high high high low low low exedg timer internal bus circuit1 edge detect circuit2 circuit 1 output compare register 2 input capture register 1 input capture register 2 cc[1:0] counter pin pin pin pin pin register register note: if ic, oc and to interrupt requests have separate vectors then the last or is not present (see device interrupt vector table) (see note)
st72311r, st72511r, st72512r, st72532r 63/164 16-bit timer (cont'd) 16-bit read sequence: (from either the counter register or the alternate counter register). the user must read the ms byte first, then the ls byte value is buffered automatically. this buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the ms byte several times. after a complete reading sequence, if only the clr register or aclr register are read, they re- turn the ls byte of the count value at the time of the read. whatever the timer mode used (input capture, out- put compare, one pulse mode or pwm mode) an overflow occurs when the counter rolls over from ffffh to 0000h then: the tof bit of the sr register is set. a timer interrupt is generated if: toie bit of the cr1 register is set and i bit of the cc register is cleared. if one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. clearing the overflow interrupt request is done in two steps: 1. reading the sr register while the tof bit is set. 2. an access (read or write) to the clr register. notes: the tof bit is not cleared by accesses to aclr register. the advantage of accessing the aclr register rather than the clr register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the tof bit erroneously. the timer is not affected by wait mode. in halt mode, the counter stops counting until the mode is exited. counting then resumes from the previous count (mcu awakened by an interrupt) or from the reset count (mcu awakened by a reset). 10.4.3.2 external clock the external clock (where available) is selected if cc0=1 and cc1=1 in cr2 register. the status of the exedg bit in the cr2 register determines the type of level transition on the exter- nal clock pin extclk that will trigger the free run- ning counter. the counter is synchronised with the falling edge of the internal cpu clock. a minimum of four falling edges of the cpu clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the cpu clock frequency. is buffered read at t0 read returns the buffered ls byte value at t0 at t0 + d t other instructions beginning of the sequence sequence completed ls byte ls byte ms byte
st72311r, st72511r, st72512r, st72532r 64/164 16-bit timer (cont'd) figure 36. counter timing diagram, internal clock divided by 2 figure 37. counter timing diagram, internal clock divided by 4 figure 38. counter timing diagram, internal clock divided by 8 note: the mcu is in reset state when the internal reset signal is high, when it is low the mcu is running. cpu clock fffd fffe ffff 0000 0001 0002 0003 internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000 0001 cpu clock internal reset timer clock counter register timer overflow flag (tof) cpu clock internal reset timer clock counter register timer overflow flag (tof) fffc fffd 0000
st72311r, st72511r, st72512r, st72532r 65/164 16-bit timer (cont'd) 10.4.3.3 input capture in this section, the index, i , may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. the two input capture 16-bit registers (ic1r and ic2r) are used to latch the value of the free run- ning counter after a transition detected by the icap i pin (see figure 5). ic i r register is a read-only register. the active transition is software programmable through the iedg i bit of control registers (cr i ). timing resolution is one count of the free running counter: ( f cpu / cc[1:0]). procedure: to use the input capture function select the follow- ing in the cr2 register: select the timer clock (cc[1:0]) (see table 18 clock control bits). select the edge of the active transition on the icap2 pin with the iedg2 bit (the icap2 pin must be configured as floating input). and select the following in the cr1 register: set the icie bit to generate an interrupt after an input capture coming from either the icap1 pin or the icap2 pin select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1pin must be configured as floating input). when an input capture occurs: icf i bit is set. the ic i r register contains the value of the free running counter on the active transition on the icap i pin (see figure 40). a timer interrupt is generated if the icie bit is set and the i bit is cleared in the cc register. other- wise, the interrupt remains pending until both conditions become true. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. notes: 1. after reading the ic i hr register, transfer of input capture data is inhibited and icf i will never be set until the ic i lr register is also read. 2. the ic i r register contains the free running counter value which corresponds to the most recent input capture. 3. the 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. in one pulse mode and pwm mode only the input capture 2 can be used. 5. the alternate inputs (icap1 & icap2) are always directly connected to the timer. so any transitions on these pins activate the input cap- ture function. moreover if one of the icap i pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the icie bit is set. this can be avoided if the input capture func- tion i is disabled by reading the ic i hr (see note 1). 6. the tof bit can be used with interrupt in order to measure event that go beyond the timer range (ffffh). ms byte ls byte icir ic i hr ic i lr
st72311r, st72511r, st72512r, st72532r 66/164 16-bit timer (cont'd) figure 39. input capture block diagram figure 40. input capture timing diagram icie cc0 cc1 16-bit free running counter iedg1 (control register 1) cr1 (control register 2) cr2 icf2 icf1 0 0 0 (status register) sr iedg2 icap1 icap2 edge detect circuit2 16-bit ic1r register ic2r register edge detect circuit1 pin pin ff01 ff02 ff03 ff03 timer clock counter register icapi pin icapi flag icapi register note: a ctive edge is rising edge.
st72311r, st72511r, st72512r, st72532r 67/164 16-bit timer (cont'd) 10.4.3.4 output compare in this section, the index, i , may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. this function can be used to control an output waveform or indicate when a period of time has elapsed. when a match is found between the output com- pare register and the free running counter, the out- put compare function: assigns pins with a programmable value if the ocie bit is set sets a flag in the status register generates an interrupt if enabled two 16-bit registers output compare register 1 (oc1r) and output compare register 2 (oc2r) contain the value to be compared to the counter register each timer clock cycle. these registers are readable and writable and are not affected by the timer hardware. a reset event changes the oc i r value to 8000h. timing resolution is one count of the free running counter: ( f cpu/ cc[1:0] ). procedure: to use the output compare function, select the fol- lowing in the cr2 register: set the oc i e bit if an output is needed then the ocmp i pin is dedicated to the output compare i signal. select the timer clock (cc[1:0]) (see table 18 clock control bits). and select the following in the cr1 register: select the olvl i bit to applied to the ocmp i pins after the match occurs. set the ocie bit to generate an interrupt if it is needed. when a match is found between ocri register and cr register: ocf i bit is set. the ocmp i pin takes olvl i bit value (ocmp i pin latch is forced low during reset). a timer interrupt is generated if the ocie bit is set in the cr2 register and the i bit is cleared in the cc register (cc). the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: d t = output compare period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 de- pending on cc[1:0] bits, see table 18 clock control bits) if the timer clock is an external clock, the formula is: where: d t = output compare period (in seconds) f ext = external timer clock frequency (in hertz) clearing the output compare interrupt request (i.e. clearing the ocf i bit) is done by: 1. reading the sr register while the ocf i bit is set. 2. an access (read or write) to the oc i lr register. the following procedure is recommended to pre- vent the ocf i bit from being set between the time it is read and the write to the oc i r register: write to the oc i hr register (further compares are inhibited). read the sr register (first step of the clearance of the ocf i bit, which may be already set). write to the oc i lr register (enables the output compare function and clears the ocf i bit). ms byte ls byte oc i roc i hr oc i lr d oc i r= d t * f cpu presc d oc i r= d t * f ext
st72311r, st72511r, st72512r, st72532r 68/164 16-bit timer (cont'd) notes: 1. after a processor write cycle to the oc i hr reg- ister, the output compare function is inhibited until the oc i lr register is also written. 2. if the oc i e bit is not set, the ocmp i pin is a general i/o port and the olvl i bit will not appear when a match is found but an interrupt could be generated if the ocie bit is set. 3. when the timer clock is f cpu /2, ocf i and ocmp i are set while the counter value equals the oc i r register value (see figure 42 on page 68). this behaviour is the same in opm or pwm mode. when the timer clock is f cpu /4, f cpu /8 or in external clock mode, ocf i and ocmp i are set while the counter value equals the oc i r regis- ter value plus 1 (see figure 43 on page 68). 4. the output compare functions can be used both for generating external events on the ocmp i pins even if the input capture mode is also used. 5. the value in the 16-bit oc i r register and the olv i bit should be changed after each suc- cessful comparison in order to control an output waveform or establish a new elapsed timeout. forced compare output capability when the folv i bit is set by software, the olvl i bit is copied to the ocmp i pin. the olv i bit has to be toggled in order to toggle the ocmp i pin when it is enabled (oc i e bit=1). the ocf i bit is then not set by hardware, and thus no interrupt request is generated. folvl i bits have no effect in both one pulse mode and pwm mode. figure 41. output compare block diagram output compare 16-bit circuit oc1r register 16 bit free running counter oc1e cc0 cc1 oc2e olvl1 olvl2 ocie (control register 1) cr1 (control register 2) cr2 0 0 0 ocf2 ocf1 (status register) sr 16-bit 16-bit ocmp1 ocmp2 latch 1 latch 2 oc2r register pin pin folv2 folv1
st72311r, st72511r, st72512r, st72532r 69/164 16-bit timer (cont'd) figure 42. output compare timing diagram, f timer =f cpu /2 figure 43. output compare timing diagram, f timer =f cpu /4 internal cpu clock timer clock counter register output compare register i (ocr i ) output compare flag i (ocf i ) ocmp i pin (olvl i =1) 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf internal cpu clock timer clock counter register output compare register i (ocr i ) compare register i latch 2ed3 2ed0 2ed1 2ed2 2ed3 2ed4 2ecf ocmp i pin (olvl i =1) output compare flag i (ocf i )
st72311r, st72511r, st72512r, st72532r 70/164 16-bit timer (cont'd) 10.4.3.5 one pulse mode one pulse mode enables the generation of a pulse when an external event occurs. this mode is selected via the opm bit in the cr2 register. the one pulse mode uses the input capture1 function and the output compare1 function. procedure: to use one pulse mode: 1. load the oc1r register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after the pulse. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin during the pulse. select the edge of the active transition on the icap1 pin with the iedg1 bit (the icap1 pin must be configured as floating input). 3. select the following in the cr2 register: set the oc1e bit, the ocmp1 pin is then ded- icated to the output compare 1 function. set the opm bit. select the timer clock cc[1:0] (see table 18 clock control bits). then, on a valid event on the icap1 pin, the coun- ter is initialized to fffch and olvl2 bit is loaded on the ocmp1 pin, the icf1 bit is set and the val- ue fffdh is loaded in the ic1r register. because the icf1 bit is set when an active edge occurs, an interrupt can be generated if the icie bit is set. clearing the input capture interrupt request (i.e. clearing the icf i bit) is done in two steps: 1. reading the sr register while the icf i bit is set. 2. an access (read or write) to the ic i lr register. the oc1r register value required for a specific timing application can be calculated using the fol- lowing formula: where: t = pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on the cc[1:0] bits, see table 18 clock control bits) if the timer clock is an external clock the formula is: where: t = pulse period (in seconds) f ext = external timer clock frequency (in hertz) when the value of the counter is equal to the value of the contents of the oc1r register, the olvl1 bit is output on the ocmp1 pin, (see figure 44). notes: 1. the ocf1 bit cannot be set by hardware in one pulse mode but the ocf2 bit can generate an output compare interrupt. 2. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. 3. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. 4. the icap1 pin can not be used to perform input capture. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the icap1 pin and icf1 can also generates interrupt if icie is set. 5. when one pulse mode is used oc1r is dedi- cated to this mode. nevertheless oc2r and ocf2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level olvl2 is dedi- cated to the one pulse mode. event occurs counter = oc1r ocmp1 = olvl1 when when on icap1 one pulse mode cycle ocmp1 = olvl2 counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc -5 oc i r= t * f ext -5
st72311r, st72511r, st72512r, st72532r 71/164 16-bit timer (cont'd) figure 44. one pulse mode timing example figure 45. pulse width modulation mode timing example counter fffc fffd fffe 2ed0 2ed1 2ed2 2ed3 fffc fffd olvl2 olvl2 olvl1 icap1 ocmp1 compare1 note: iedg1=1, oc1r=2ed0h, olvl1=0, olvl2=1 counter 34e2 34e2 fffc olvl2 olvl2 olvl1 ocmp1 compare2 compare1 compare2 note: oc1r=2ed0h, oc2r=34e2, olvl1=0, olvl2= 1 fffc fffd fffe 2ed0 2ed1 2ed2
st72311r, st72511r, st72512r, st72532r 72/164 16-bit timer (cont'd) 10.4.3.6 pulse width modulation mode pulse width modulation (pwm) mode enables the generation of a signal with a frequency and pulse length determined by the value of the oc1r and oc2r registers. the pulse width modulation mode uses the com- plete output compare 1 function plus the oc2r register, and so these functionality can not be used when the pwm mode is activated. procedure to use pulse width modulation mode: 1. load the oc2r register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. load the oc1r register with the value corre- sponding to the period of the pulse if (olvl1=0 and olvl2=1) using the formula in the oppo- site column. 3. select the following in the cr1 register: using the olvl1 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc1r register. using the olvl2 bit, select the level to be ap- plied to the ocmp1 pin after a successful comparison with oc2r register. 4. select the following in the cr2 register: set oc1e bit: the ocmp1 pin is then dedicat- ed to the output compare 1 function. set the pwm bit. select the timer clock (cc[1:0]) (see table 18 clock control bits). if olvl1=1 and olvl2=0 the length of the posi- tive pulse is the difference between the oc2r and oc1r registers. if olvl1=olvl2 a continuous signal will be seen on the ocmp1 pin. the oc i r register value required for a specific tim- ing application can be calculated using the follow- ing formula: where: t = signal or pulse period (in seconds) f cpu = cpu clock frequency (in hertz) presc = timer prescaler factor (2, 4 or 8 depend- ing on cc[1:0] bits, see table 18 clock control bits) if the timer clock is an external clock the formula is: where: t = signal or pulse period (in seconds) f ext = external timer clock frequency (in hertz) the output compare 2 event causes the counter to be initialized to fffch (see figure 45) notes: 1. after a write instruction to the oc i hr register, the output compare function is inhibited until the oc i lr register is also written. 2. the ocf1 and ocf2 bits cannot be set by hardware in pwm mode therefore the output compare interrupt is inhibited. 3. the icf1 bit is set by hardware when the coun- ter reaches the oc2r value and can produce a timer interrupt if the icie bit is set and the i bit is cleared. 4. in pwm mode the icap1 pin can not be used to perform input capture because it is discon- nected to the timer. the icap2 pin can be used to perform input capture (icf2 can be set and ic2r can be loaded) but the user must take care that the counter is reset each period and icf1 can also generates interrupt if icie is set. 5. when the pulse width modulation (pwm) and one pulse mode (opm) bits are both set, the pwm mode is the only active one. counter ocmp1 = olvl2 counter = oc2r ocmp1 = olvl1 when when = oc1r pulse width modulation cycle counter is reset to fffch icf1 bit is set oc i r value = t * f cpu presc -5 oc i r= t * f ext -5
st72311r, st72511r, st72512r, st72532r 73/164 16-bit timer (cont'd) 10.4.4 low power modes 10.4.5 interrupts note: the 16-bit timer interrupt events are connected to the same interrupt vector (see interrupts chap- ter). these events generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). 10.4.6 summary of timer modes 1) see note 4 in section 10.4.3.5 oone pulse modeo on page 69 2) see note 5 in section 10.4.3.5 oone pulse modeo on page 69 3) see note 4 in section 10.4.3.6 opulse width modulation modeo on page 71 mode description wait no effect on 16-bit timer. timer interrupts cause the device to exit from wait mode. halt 16-bit timer registers are frozen. in halt mode, the counter stops counting until halt mode is exited. counting resumes from the previous count when the mcu is woken up by an interrupt with aexit from halt modeo capability or from the counter reset value when the mcu is woken up by a reset. if an input capture event occurs on the icap i pin, the input capture detection circuitry is armed. consequent- ly, when the mcu is woken up by an interrupt with aexit from halt modeo capability, the icf i bit is set, and the counter value present when exiting from halt mode is captured into the ic i r register. interrupt event event flag enable control bit exit from wait exit from halt input capture 1 event/counter reset in pwm mode icf1 icie yes no input capture 2 event icf2 yes no output compare 1 event (not available in pwm mode) ocf1 ocie yes no output compare 2 event (not available in pwm mode) ocf2 yes no timer overflow event tof toie yes no modes available resources input capture 1 input capture 2 output compare 1 output compare 2 input capture (1 and/or 2) yes yes yes yes output compare (1 and/or 2) yes yes yes yes one pulse mode no not recommended 1) no partially 2) pwm mode no not recommended 3) no no
st72311r, st72511r, st72512r, st72532r 74/164 16-bit timer (cont'd) 10.4.7 register description each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. control register 1 (cr1) read/write reset value: 0000 0000 (00h) bit 7 = icie input capture interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the icf1 or icf2 bit of the sr register is set. bit 6 = ocie output compare interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is generated whenever the ocf1 or ocf2 bit of the sr register is set. bit 5 = toie timer overflow interrupt enable. 0: interrupt is inhibited. 1: a timer interrupt is enabled whenever the tof bit of the sr register is set. bit 4 = folv2 forced output compare 2. this bit is set and cleared by software. 0: no effect on the ocmp2 pin. 1: forces the olvl2 bit to be copied to the ocmp2 pin, if the oc2e bit is set and even if there is no successful comparison. bit 3 = folv1 forced output compare 1. this bit is set and cleared by software. 0: no effect on the ocmp1 pin. 1: forces olvl1 to be copied to the ocmp1 pin, if the oc1e bit is set and even if there is no suc- cessful comparison. bit 2 = olvl2 output level 2. this bit is copied to the ocmp2 pin whenever a successful comparison occurs with the oc2r reg- ister and ocxe is set in the cr2 register. this val- ue is copied to the ocmp1 pin in one pulse mode and pulse width modulation mode. bit 1 = iedg1 input edge 1. this bit determines which type of level transition on the icap1 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = olvl1 output level 1. the olvl1 bit is copied to the ocmp1 pin when- ever a successful comparison occurs with the oc1r register and the oc1e bit is set in the cr2 register. 70 icie ocie toie folv2 folv1 olvl2 iedg1 olvl1
st72311r, st72511r, st72512r, st72532r 75/164 16-bit timer (cont'd) control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = oc1e output compare 1 pin enable. this bit is used only to output the signal from the timer on the ocmp1 pin (olv1 in output com- pare mode, both olv1 and olv2 in pwm and one-pulse mode). whatever the value of the oc1e bit, the output compare 1 function of the timer re- mains active. 0: ocmp1 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp1 pin alternate function enabled. bit 6 = oc2e output compare 2 pin enable. this bit is used only to output the signal from the timer on the ocmp2 pin (olv2 in output com- pare mode). whatever the value of the oc2e bit, the output compare 2 function of the timer re- mains active. 0: ocmp2 pin alternate function disabled (i/o pin free for general-purpose i/o). 1: ocmp2 pin alternate function enabled. bit 5 = opm one pulse mode. 0: one pulse mode is not active. 1: one pulse mode is active, the icap1 pin can be used to trigger one pulse on the ocmp1 pin; the active transition is given by the iedg1 bit. the length of the generated pulse depends on the contents of the oc1r register. bit 4 = pwm pulse width modulation. 0: pwm mode is not active. 1: pwm mode is active, the ocmp1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of oc1r register; the period depends on the value of oc2r regis- ter. bit 3, 2 = cc[1:0] clock control. the timer clock mode depends on these bits: table 18. clock control bits note : if the external clock pin is not available, pro- gramming the external clock configuration stops the counter. bit 1 = iedg2 input edge 2. this bit determines which type of level transition on the icap2 pin will trigger the capture. 0: a falling edge triggers the capture. 1: a rising edge triggers the capture. bit 0 = exedg external clock edge. this bit determines which type of level transition on the external clock pin extclk will trigger the counter register. 0: a falling edge triggers the counter register. 1: a rising edge triggers the counter register. 70 oc1e oc2e opm pwm cc1 cc0 iedg2 exedg timer clock cc1 cc0 f cpu /4 0 0 f cpu /2 0 1 f cpu /8 1 0 external clock (where available) 11
st72311r, st72511r, st72512r, st72532r 76/164 16-bit timer (cont'd) status register (sr) read only reset value: 0000 0000 (00h) the three least significant bits are not used. bit 7 = icf1 input capture flag 1. 0: no input capture (reset value). 1: an input capture has occurred on the icap1 pin or the counter has reached the oc2r value in pwm mode. to clear this bit, first read the sr register, then read or write the low byte of the ic1r (ic1lr) register. bit 6 = ocf1 output compare flag 1. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc1r register. to clear this bit, first read the sr register, then read or write the low byte of the oc1r (oc1lr) reg- ister. bit 5 = tof timer overflow flag. 0: no timer overflow (reset value). 1: the free running counter rolled over from ffffh to 0000h. to clear this bit, first read the sr reg- ister, then read or write the low byte of the cr (clr) register. note: reading or writing the aclr register does not clear tof. bit 4 = icf2 input capture flag 2. 0: no input capture (reset value). 1: an input capture has occurred on the icap2 pin. to clear this bit, first read the sr register, then read or write the low byte of the ic2r (ic2lr) register. bit 3 = ocf2 output compare flag 2. 0: no match (reset value). 1: the content of the free running counter has matched the content of the oc2r register. to clear this bit, first read the sr register, then read or write the low byte of the oc2r (oc2lr) reg- ister. bit 2-0 = reserved, forced by hardware to 0. input capture 1 high register (ic1hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). input capture 1 low register (ic1lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). output compare 1 high register (oc1hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 1 low register (oc1lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. 70 icf1 ocf1 tof icf2 ocf2 0 0 0 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72311r, st72511r, st72512r, st72532r 77/164 16-bit timer (cont'd) output compare 2 high register (oc2hr) read/write reset value: 1000 0000 (80h) this is an 8-bit register that contains the high part of the value to be compared to the chr register. output compare 2 low register (oc2lr) read/write reset value: 0000 0000 (00h) this is an 8-bit register that contains the low part of the value to be compared to the clr register. counter high register (chr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. counter low register (clr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after accessing the sr register clears the tof bit. alternate counter high register (achr) read only reset value: 1111 1111 (ffh) this is an 8-bit register that contains the high part of the counter value. alternate counter low register (aclr) read only reset value: 1111 1100 (fch) this is an 8-bit register that contains the low part of the counter value. a write to this register resets the counter. an access to this register after an access to sr register does not clear the tof bit in sr register. input capture 2 high register (ic2hr) read only reset value: undefined this is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 2 event). input capture 2 low register (ic2lr) read only reset value: undefined this is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 2 event). 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb 70 msb lsb
st72311r, st72511r, st72512r, st72532r 78/164 16-bit timer (cont'd) table 19. 16-bit timer register map and reset values address (hex.) register label 76543210 timer a: 32 timer b: 42 cr1 reset value icie 0 ocie 0 toie 0 folv2 0 folv1 0 olvl2 0 iedg1 0 olvl1 0 timer a: 31 timer b: 41 cr2 reset value oc1e 0 oc2e 0 opm 0 pwm 0 cc1 0 cc0 0 iedg2 0 exedg 0 timer a: 33 timer b: 43 sr reset value icf1 0 ocf1 0 tof 0 icf2 0 ocf2 0 - 0 - 0 - 0 timer a: 34 timer b: 44 ichr1 reset value msb - ------ lsb - timer a: 35 timer b: 45 iclr1 reset value msb - ------ lsb - timer a: 36 timer b: 46 ochr1 reset value msb - ------ lsb - timer a: 37 timer b: 47 oclr1 reset value msb - ------ lsb - timer a: 3e timer b: 4e ochr2 reset value msb - ------ lsb - timer a: 3f timer b: 4f oclr2 reset value msb - ------ lsb - timer a: 38 timer b: 48 chr reset value msb 1111111 lsb 1 timer a: 39 timer b: 49 clr reset value msb 1111110 lsb 0 timer a: 3a timer b: 4a achr reset value msb 1111111 lsb 1 timer a: 3b timer b: 4b aclr reset value msb 1111110 lsb 0 timer a: 3c timer b: 4c ichr2 reset value msb - ------ lsb - timer a: 3d timer b: 4d iclr2 reset value msb - ------ lsb -
st72311r, st72511r, st72512r, st72532r 79/164 10.5 serial peripheral interface (spi) 10.5.1 introduction the serial peripheral interface (spi) allows full- duplex, synchronous, serial communication with external devices. an spi system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves. the spi is normally used for communication be- tween the microcontroller and external peripherals or another microcontroller. refer to the pin description chapter for the device- specific pin-out. 10.5.2 main features n full duplex, three-wire synchronous transfers n master or slave operation n four master mode frequencies n maximum slave mode frequency = fcpu/2. n four programmable master bit rates n programmable clock polarity and phase n end of transfer interrupt flag n write collision flag protection n master mode fault protection capability. 10.5.3 general description the spi is connected to external devices through 4 alternate pins: miso: master in slave out pin mosi: master out slave in pin sck: serial clock pin ss: slave select pin a basic example of interconnections between a single master and a single slave is illustrated on figure 46. the mosi pins are connected together as are miso pins. in this way data is transferred serially between master and slave (most significant bit first). when the master device transmits data to a slave device via mosi pin, the slave device responds by sending data to the master device via the miso pin. this implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master de- vice via the sck pin). thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. a status flag is used to indicate that the i/o operation is com- plete. four possible data/clock timing relationships may be chosen (see figure 49) but master and slave must be programmed with the same timing mode. figure 46. serial peripheral interface master/slave 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master ss ss +5v msbit lsbit msbit lsbit
st72311r, st72511r, st72512r, st72532r 80/164 serial peripheral interface (cont'd) figure 47. serial peripheral interface block diagram dr read buffer 8-bit shift register write read internal bus spi spie spe spr2 mstr cpha spr0 spr1 cpol spif wcol modf serial clock generator mosi miso ss sck control state cr sr - -- -- it request master control
st72311r, st72511r, st72512r, st72532r 81/164 serial peripheral interface (cont'd) 10.5.4 functional description figure 46 shows the serial peripheral interface (spi) block diagram. this interface contains 3 dedicated registers: a control register (cr) a status register (sr) a data register (dr) refer to the cr, sr and dr registers in section 10.5.7for the bit definitions. 10.5.4.1 master configuration in a master configuration, the serial clock is gener- ated on the sck pin. procedure select the spr0 & spr1 bits to define the se- rial clock baud rate (see cr register). select the cpol and cpha bits to define one of the four relationships between the data transfer and the serial clock (see figure 49). the ss pin must be connected to a high level signal during the complete byte transmit se- quence. the mstr and spe bits must be set (they re- main set only if the ss pin is connected to a high level signal). in this configuration the mosi pin is a data output and to the miso pin is a data input. transmit sequence the transmit sequence begins when a byte is writ- ten the dr register. the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the mosi pin most significant bit first. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if the spie bit is set and the i bit in the ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set 2. a write or a read of the dr register. note: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read.
st72311r, st72511r, st72512r, st72532r 82/164 serial peripheral interface (cont'd) 10.5.4.2 slave configuration in slave configuration, the serial clock is received on the sck pin from the master device. the value of the spr0 & spr1 bits is not used for the data transfer. procedure for correct data transfer, the slave device must be in the same timing mode as the mas- ter device (cpol and cpha bits). see figure 49. the ss pin must be connected to a low level signal during the complete byte transmit se- quence. clear the mstr bit and set the spe bit to as- sign the pins to alternate function. in this configuration the mosi pin is a data input and the miso pin is a data output. transmit sequence the data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the miso pin most significant bit first. the transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its mosi pin. when data transfer is complete: the spif bit is set by hardware an interrupt is generated if spie bit is set and i bit in ccr register is cleared. during the last clock cycle the spif bit is set, a copy of the data byte received in the shift register is moved to a buffer. when the dr register is read, the spi peripheral returns this buffered value. clearing the spif bit is performed by the following software sequence: 1. an access to the sr register while the spif bit is set. 2. a write or a read of the dr register. notes: while the spif bit is set, all writes to the dr register are inhibited until the sr register is read. the spif bit can be cleared during a second transmission; however, it must be cleared before the second spif bit in order to prevent an overrun condition (see section 10.5.4.6). depending on the cpha bit, the ss pin has to be set to write to the dr register between each data byte transfer to avoid a write collision (see section 10.5.4.4).
st72311r, st72511r, st72512r, st72532r 83/164 serial peripheral interface (cont'd) 10.5.4.3 data transfer format during an spi transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). the serial clock is used to syn- chronize the data transfer during a sequence of eight clock pulses. the ss pin allows individual selection of a slave device; the other slave devices that are not select- ed do not interfere with the spi transfer. clock phase and clock polarity four possible timing relationships may be chosen by software, using the cpol and cpha bits. the cpol (clock polarity) bit controls the steady state value of the clock when no data is being transferred. this bit affects both master and slave modes. the combination between the cpol and cpha (clock phase) bits selects the data capture clock edge. figure 49, shows an spi transfer with the four combinations of the cpha and cpol bits. the di- agram may be interpreted as a master or slave timing diagram where the sck pin, the miso pin, the mosi pin are directly connected between the master and the slave device. the ss pin is the slave device select input and can be driven by the master device. the master device applies data to its mosi pin- clock edge before the capture clock edge. cpha bit is set the second edge on the sck pin (falling edge if the cpol bit is reset, rising edge if the cpol bit is set) is the msbit capture strobe. data is latched on the occurrence of the second clock transition. no write collision should occur even if the ss pin stays low during a transfer of several bytes (see figure 48). cpha bit is reset the first edge on the sck pin (falling edge if cpol bit is set, rising edge if cpol bit is reset) is the msbit capture strobe. data is latched on the oc- currence of the first clock transition. the ss pin must be toggled high and low between each byte transmitted (see figure 48). to protect the transmission from a write collision a low value on the ss pin of a slave device freezes the data in its dr register and does not allow it to be altered. therefore the ss pin must be high to write a new data byte in the dr without producing a write collision. figure 48. cpha / ss timing diagram mosi/miso master ss slave ss (cpha=0) slave ss (cpha=1) byte 1 byte 2 byte 3 vr02131a
st72311r, st72511r, st72512r, st72532r 84/164 serial peripheral interface (cont'd) figure 49. data clock timing diagram cpol = 1) cpol = 0) miso (from master) mosi (from slave) ss (to slave) capture strobe cpha =1 cpol = 1 cpol = 0 msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit miso (from master) mosi ss (to slave) capture strobe cpha =0 note: this figure should not be used as a replacement for parametric information. refer to the electrical characteristics chapter. (from slave) vr02131b msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit msbit bit 6 bit 5 bit 4 bit3 bit 2 bit 1 lsbit sclk (with sclk (with
st72311r, st72511r, st72512r, st72532r 85/164 serial peripheral interface (cont'd) 10.5.4.4 write collision error a write collision occurs when the software tries to write to the dr register while a data transfer is tak- ing place with an external device. when this hap- pens, the transfer continues uninterrupted; and the software write will be unsuccessful. write collisions can occur both in master and slave mode. note: a oread collisiono will never occur since the received data byte is placed in a buffer in which access is always synchronous with the mcu oper- ation. in slave mode when the cpha bit is set: the slave device will receive a clock (sck) edge prior to the latch of the first data transfer. this first clock edge will freeze the data in the slave device dr register and output the msbit on to the exter- nal miso pin of the slave device. the ss pin low state enables the slave device but the output of the msbit onto the miso pin does not take place until the first data transfer clock edge. when the cpha bit is reset: data is latched on the occurrence of the first clock transition. the slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the dr register after its ss pin has been pulled low. for this reason, the ss pin must be high, between each data byte transfer, to allow the cpu to write in the dr register without generating a write colli- sion. in master mode collision in the master device is defined as a write of the dr register while the internal serial clock (sck) is in the process of transfer. the ss pin signal must be always high on the master device. wcol bit the wcol bit in the sr register is set if a write collision occurs. no spi interrupt is generated when the wcol bit is set (the wcol bit is a status flag only). clearing the wcol bit is done through a software sequence (see figure 50). figure 50. clearing the wcol bit (write collision flag) software sequence clearing sequence after spif = 1 (end of a data byte transfer) 1st step read sr read dr write dr 2nd step spif =0 wcol=0 spif =0 wcol=0 if no transfer has started wcol=1 if a transfer has started clearing sequence before spif = 1 (during a data byte transfer) 1st step 2nd step wcol=0 before the 2nd step read sr read dr note: writing in dr register in- stead of reading in it do not reset wcol bit read sr or then then then
st72311r, st72511r, st72512r, st72532r 86/164 serial peripheral interface (cont'd) 10.5.4.5 master mode fault master mode fault occurs when the master device has its ss pin pulled low, then the modf bit is set. master mode fault affects the spi peripheral in the following ways: the modf bit is set and an spi interrupt is generated if the spie bit is set. the spe bit is reset. this blocks all output from the device and disables the spi periph- eral. the mstr bit is reset, thus forcing the device into slave mode. clearing the modf bit is done through a software sequence: 1. a read or write access to the sr register while the modf bit is set. 2. a write to the cr register. notes: to avoid any multiple slave conflicts in the case of a system comprising several mcus, the ss pin must be pulled high during the clearing se- quence of the modf bit. the spe and mstr bits may be restored to their original state during or af- ter this clearing sequence. hardware does not allow the user to set the spe and mstr bits while the modf bit is set except in the modf bit clearing sequence. in a slave device the modf bit can not be set, but in a multi master configuration the device can be in slave mode with this modf bit set. the modf bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine. 10.5.4.6 overrun condition an overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the byte sent after the spif bit was last cleared. a read to the dr register returns this byte. all other bytes are lost. this condition is not detected by the spi peripher- al.
st72311r, st72511r, st72512r, st72532r 87/164 serial peripheral interface (cont'd) 10.5.4.7 single master and multimaster configurations there are two types of spi systems: single master system multimaster system single master system a typical single master system may be configured, using an mcu as the master and four mcus as slaves (see figure 51). the master device selects the individual slave de- vices by using four pins of a parallel port to control the four ss pins of the slave devices. the ss pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices. note: to prevent a bus conflict on the miso line the master allows only one active slave device during a transmission. for more security, the slave device may respond to the master with the received data byte. then the master will receive the previous byte back from the slave device if all miso and mosi pins are con- nected and the slave has not written its dr regis- ter. other transmission security methods can use ports for handshake lines or data bytes with com- mand fields. multi-master system a multi-master system may also be configured by the user. transfer of master control could be im- plemented using a handshake method through the i/o ports or by an exchange of code messages through the serial peripheral interface system. the multi-master system is principally handled by the mstr bit in the cr register and the modf bit in the sr register. figure 51. single master configuration miso mosi mosi mosi mosi mosi miso miso miso miso ss ss ss ss ss sck sck sck sck sck 5v ports slave mcu slave mcu slave mcu slave mcu master mcu
st72311r, st72511r, st72512r, st72532r 88/164 serial peripheral interface (cont'd) 10.5.5 low power modes 10.5.6 interrupts note : the spi interrupt events are connected to the same interrupt vector (see interrupts chapter). they generate an interrupt if the corresponding enable control bit is set and the interrupt mask in the cc register is reset (rim instruction). mode description wait no effect on spi. spi interrupt events cause the device to exit from wait mode. halt spi registers are frozen. in halt mode, the spi is inactive. spi operation resumes when the mcu is woken up by an interrupt with aexit from halt modeo capability. interrupt event event flag enable control bit exit from wait exit from halt spi end of transfer event spif spie yes no master mode fault event modf yes no
st72311r, st72511r, st72512r, st72532r 89/164 serial peripheral interface (cont'd) 10.5.7 register description control register (cr) read/write reset value: 0000xxxx (0xh) bit 7 = spie serial peripheral interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an spi interrupt is generated whenever spif=1 or modf=1 in the sr register bit 6 = spe serial peripheral output enable. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 10.5.4.5 omaster mode faulto on page 85). 0: i/o port connected to pins 1: spi alternate functions connected to pins the spe bit is cleared by reset, so the spi periph- eral is not initially connected to the external pins. bit 5 = spr2 divider enable . this bit is set and cleared by software and it is cleared by reset. it is used with the spr[1:0] bits to set the baud rate. refer to table 20. 0: divider by 2 enabled 1: divider by 2 disabled bit 4 = mstr master. this bit is set and cleared by software. it is also cleared by hardware when, in master mode, ss=0 (see section 10.5.4.5 omaster mode faulto on page 85). 0: slave mode is selected 1: master mode is selected, the function of the sck pin changes from an input to an output and the functions of the miso and mosi pins are re- versed. bit 3 = cpol clock polarity. this bit is set and cleared by software. this bit de- termines the steady state of the serial clock. the cpol bit affects both the master and slave modes. 0: the steady state is a low value at the sck pin. 1: the steady state is a high value at the sck pin. bit 2 = cpha clock phase. this bit is set and cleared by software. 0: the first clock transition is the first data capture edge. 1: the second clock transition is the first capture edge. bit 1:0 = spr[1 : 0] serial peripheral rate. these bits are set and cleared by software.used with the spr2 bit, they select one of six baud rates to be used as the serial clock when the device is a master. these 2 bits have no effect in slave mode. table 20. serial peripheral baud rate 70 spie spe spr2 mstr cpol cpha spr1 spr0 serial clock spr2 spr1 spr0 f cpu /2 1 0 0 f cpu /8 0 0 0 f cpu /16 0 0 1 f cpu /32 1 1 0 f cpu /64 0 1 0 f cpu /128 0 1 1
st72311r, st72511r, st72512r, st72532r 90/164 serial peripheral interface (cont'd) status register (sr) read only reset value: 0000 0000 (00h) bit 7 = spif serial peripheral data transfer flag. this bit is set by hardware when a transfer has been completed. an interrupt is generated if spie=1 in the cr register. it is cleared by a soft- ware sequence (an access to the sr register fol- lowed by a read or write to the dr register). 0: data transfer is in progress or has been ap- proved by a clearing sequence. 1: data transfer between the device and an exter- nal device has been completed. note: while the spif bit is set, all writes to the dr register are inhibited. bit 6 = wcol write collision status. this bit is set by hardware when a write to the dr register is done during a transmit sequence. it is cleared by a software sequence (see figure 50). 0: no write collision occurred 1: a write collision has been detected bit 5 = unused. bit 4 = modf mode fault flag. this bit is set by hardware when the ss pin is pulled low in master mode (see section 10.5.4.5 omaster mode faulto on page 85). an spi interrupt can be generated if spie=1 in the cr register. this bit is cleared by a software sequence (an ac- cess to the sr register while modf=1 followed by a write to the cr register). 0: no master mode fault detected 1: a fault in master mode has been detected bits 3-0 = unused. data i/o register (dr) read/write reset value: undefined the dr register is used to transmit and receive data on the serial bus. in the master device only a write to this register will initiate transmission/re- ception of another byte. notes: during the last clock cycle the spif bit is set, a copy of the received data byte in the shift register is moved to a buffer. when the user reads the serial peripheral data i/o register, the buffer is actually being read. warning: a write to the dr register places data directly into the shift register for transmission. a write to the the dr register returns the value lo- cated in the buffer and not the contents of the shift register (see figure 47 ). 70 spif wcol - modf - - - - 70 d7 d6 d5 d4 d3 d2 d1 d0
st72311r, st72511r, st72512r, st72532r 91/164 serial peripheral interface (cont'd) table 21. spi register map and reset values address (hex.) register label 76543210 0021h spidr reset value msb xxxxxxx lsb x 0022h spicr reset value spie 0 spe 0 spr2 0 mstr 0 cpol x cpha x spr1 x spr0 x 0023h spisr reset value spif 0 wcol 00 modf 00000
st72311r, st72511r, st72512r, st72532r 92/164 10.6 serial communications interface (sci) 10.6.1 introduction the serial communications interface (sci) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the sci of- fers a very wide range of baud rates using two baud rate generator systems. 10.6.2 main features n full duplex, asynchronous communications n nrz standard format (mark/space) n dual baud rate generator systems n independently programmable transmit and receive baud rates up to 250k baud. n programmable data word length (8 or 9 bits) n receive buffer full, transmit buffer empty and end of transmission flags n two receiver wake-up modes: address bit (msb) idle line n muting functionfor multiprocessor configurations n separate enable bits for transmitter and receiver n three error detection flags: overrun error noise error frame error n five interrupt sources with flags: transmit data register empty transmission complete receive data register full idle line received overrun error detected 10.6.3 general description the interface is externally connected to another device by two pins (see figure 53): tdo: transmit data output. when the transmit- ter is disabled, the output pin returns to its i/o port configuration. when the transmitter is ena- bled and nothing is to be transmitted, the tdo pin is at high level. rdi: receive data input is the serial data input. oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. through this pins, serial data is transmitted and re- ceived as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first a stop bit indicating that the frame is complete. this interface usestwo types of baud rate generator: a conventional type for commonly-used baud rates, an extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.
st72311r, st72511r, st72512r, st72532r 93/164 serial communications interface (cont'd) figure 52. sci block diagram wake up unit receive r control sr transmit control tdre tc rdrf idle or nf fe - sci control interrupt cr1 r8 t8 - m wake - -- received data register (rdr) received shift register read transmit data register (tdr) transmit shift register write rdi tdo (data regist er) dr transmit ter clock receiver clock receiver rate trans mitter rate brr scp1 f cpu control control scp0sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conven tional baud rate generator sbk rwu re te ilie rie tcie tie cr2
st72311r, st72511r, st72512r, st72532r 94/164 serial communications interface (cont'd) 10.6.4 functional description the block diagram of the serial control interface, is shown in figure 52. it contains 6 dedicated reg- isters: two control registers (cr1 & cr2) a status register (sr) a baud rate register (brr) an extended prescaler receiver register (erpr) anextendedprescaler transmitter register (etpr) refer to the register descriptions in section 10.6.7for the definitions of each bit. 10.6.4.1 serial data format word length may be selected as being either 8 or 9 bits by programming the m bit in the cr1 register (see figure 52). the tdo pin is in low state during the start bit. the tdo pin is in high state during the stop bit. an idle character is interpreted as an entire frame of a1os followed by the start bit of the next frame which contains data. a break character is interpreted on receiving a0os for some multiple of the frame period. at the end of the last break frame the transmitter inserts an ex- tra a1o bit to acknowledge the start bit. transmission and reception are driven by their own baud rate generator. figure 53. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit start bit idle frame start bit 9-bit word length (m bit is set) 8-bit word length (m bit is reset) possible parity bit possible parity bit break frame start bit extra '1' data frame break frame start bit extra '1' data frame next data frame next data frame
st72311r, st72511r, st72512r, st72532r 95/164 serial communications interface (cont'd) 10.6.4.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the m bit is set, word length is 9 bits and the 9th bit (the msb) has to be stored in the t8 bit in the cr1 reg- ister. character transmission during an sci transmission, data shifts out least significant bit first on the tdo pin. in this mode, the dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 52). procedure select the m bit to define the word length. select the desired baud rate using the brr and the etpr registers. set the te bit to assign the tdo pin to the alter- nate function and to send a idle frame as first transmission. access the sr register and write the data to send in the dr register (this sequence clears the tdre bit). repeat this sequence for each data to be transmitted. clearing the tdre bit is always performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register the tdre bit is set by hardware and it indicates: the tdr register is empty. the data transfer is beginning. the next data can be written in the dr register without overwriting the previous data. this flag generates an interrupt if the tie bit is set and the i bit is cleared in the ccr register. when a transmission is taking place, a write in- struction to the dr register stores the data in the tdr register and which is copied in the shift regis- ter at the end of the current transmission. when no transmission is taking place, a write in- struction to the dr register places the data directly in the shift register, the data transmission starts, and the tdre bit is immediately set. when a frame transmission is complete (after the stop bit or after the break frame) the tc bit is set and an interrupt is generated if the tcie is set and the i bit is cleared in the ccr register. clearing the tc bit is performed by the following software sequence: 1. an access to the sr register 2. a write to the dr register note: the tdre and tc bits are cleared by the same software sequence. break characters setting the sbk bit loads the shift register with a break character. the break frame length depends on the m bit (see figure 53). as long as the sbk bit is set, the sci send break frames to the tdo pin. after clearing this bit by software the sci insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. idle characters setting the te bit drives the sci to send an idle frame before the first data frame. clearing and then setting the te bit during a trans- mission sends an idle frame after the current word. note: resetting and setting the te bit causes the data in the tdr register to be lost. therefore the best time to toggle the te bit is when the tdre bit is set i.e. before writing the next byte in the dr.
st72311r, st72511r, st72512r, st72532r 96/164 serial communications interface (cont'd) 10.6.4.3 receiver the sci can receive data words of either 8 or 9 bits. when the m bit is set, word length is 9 bits and the msb is stored in the r8 bit in the cr1 reg- ister. character reception during a sci reception, data shifts in least signifi- cant bit first through the rdi pin. in this mode, dr register consists in a buffer (rdr) between the in- ternal bus and the received shift register (see fig- ure 52). procedure select the m bit to define the word length. select the desired baud rate using the brr and the erpr registers. set the re bit, this enables the receiver which begins searching for a start bit. when a character is received: the rdrf bit is set. it indicates that the content of the shift register is transferred to the rdr. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. clearing the rdrf bit is performed by the following software sequence done by: 1. an access to the sr register 2. a read to the dr register. the rdrf bit must be cleared before the end of the reception of the next character to avoid an overrun error. break character when a break character is received, the spi han- dles it as a framing error. idle character when a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ilie bit is set and the i bit is cleared in the ccr register. overrun error an overrun error occurs when a character is re- ceived when rdrf has not been reset. data can not be transferred from the shift register to the tdr register as long as the rdrf bit is not cleared. when a overrun error occurs: the or bit is set. the rdr content will not be lost. the shift register will be overwritten. an interrupt is generated if the rie bit is set and the i bit is cleared in the ccr register. the or bit is reset by an access to the sr register followed by a dr register read operation. noise error oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. when noise is detected in a frame: the nf is set at the rising edge of the rdrf bit. data is transferred from the shift register to the dr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the nf bit is reset by a sr register read operation followed by a dr register read operation. framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. a break is received. when the framing error is detected: the fe bit is set by hardware data is transferred from the shift register to the dr register. no interrupt is generated. however this bit rises at the same time as the rdrf bit which itself generates an interrupt. the fe bit is reset by a sr register read operation followed by a dr register read operation.
st72311r, st72511r, st72512r, st72532r 97/164 serial communications interface (cont'd) figure 54. sci baud rate and extended prescaler block diagram transmi tter receiver etpr erpr exte nded prescaler receiver rate control exte nded prescaler transmitte r rate control extended prescaler clock clock receiver rate transmit ter rate brr scp1 f cpu control control scp0sct2 sct1 sct0 scr2 scr1scr0 /2 /pr /16 conventional baud rate generator exte nded receiver prescaler register exte nded trans mitter prescale r register
st72311r, st72511r, st72512r, st72532r 98/164 serial communications interface (cont'd) 10.6.4.4 conventional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are set independently and calculated as follows: with: pr = 1, 3, 4 or 13 (see scp0 & scp1 bits) tr = 1, 2, 4, 8, 16, 32, 64,128 (see sct0, sct1 & sct2 bits) rr = 1, 2, 4, 8, 16, 32, 64,128 (see scr0,scr1 & scr2 bits) all this bits are in the brr register. example: if f cpu is 8 mhz (normal mode) and if pr=13 and tr=rr=1, the transmit and receive baud rates are 19200 baud. note: the baud rate registers must not be changed while the transmitter or the receiver is en- abled. 10.6.4.5 extended baud rate generation the extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional baud rate genera- tor retains industry standard software compatibili- ty. the extended baud rate generator block diagram is described in the figure 54. the output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the erpr or the etpr register. note: the extended prescaler is activated by set- ting the etpr or erpr register to a value other than zero. the baud rates are calculated as fol- lows: with: etpr = 1,..,255 (see etpr register) erpr = 1,.. 255 (see erpr register) 10.6.4.6 receiver muting and wake-up feature in multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant sci service overhead for all non addressed receivers. the non addressed devices may be placed in sleep mode by means of the muting function. setting the rwu bit by software puts the sci in sleep mode: all the reception status bits can not be set. all the receive interrupt are inhibited. a muted receiver may be awakened by one of the following two ways: by idle line detection if the wake bit is reset, by address mark detection if the wake bit is set. receiver wakes-up by idle line detection when the receive line has recognised an idle frame. then the rwu bit is reset by hardware but the idle bit is not set. receiver wakes-up by address mark detection when it received a a1o as the most significant bit of a word, thus indicating that the message is an ad- dress. the reception of this particular word wakes up the receiver, resets the rwu bit and sets the rdrf bit, which allows the receiver to receive this word normally and to use it as an address word. tx = (32 * pr) * tr f cpu rx = (32 * pr) * rr f cpu tx = 16 * etpr f cpu rx = 16 * erpr f cpu
st72311r, st72511r, st72512r, st72532r 99/164 serial communications interface (cont'd) 10.6.5 low power modes 10.6.6 interrupts the sci interrupt events are connected to the same interrupt vector (see interrupts chapter). these events generate an interrupt if the corre- sponding enable control bit is set and the inter- rupt mask in the cc register is reset (rim instruc- tion). mode description wait no effect on sci. sci interrupts cause the device to exit from wait mode. halt sci registers are frozen. in halt mode, the sci stops transmitting/receiving until halt mode is exited. interrupt event event flag enable control bit exit from wait exit from halt transmit data register empty tdre tie yes no transmission complete tc tcie yes no received data ready to be read rdrf rie yes no overrrun error detected or yes no idle line detected idle ilie yes no
st72311r, st72511r, st72512r, st72532r 100/164 serial communications interface (cont'd) 10.6.7 register description status register (sr) read only reset value: 1100 0000 (c0h) bit 7 = tdre transmit data register empty. this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the tie =1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: data is not transferred to the shift register 1: data is transferred to the shift register note : data will not be transferred to the shift regis- ter as long as the tdre bit is not reset. bit 6 = tc transmission complete. this bit is set by hardware when transmission of a frame containing data, a preamble or a break is complete. an interrupt is generated if tcie=1 in the cr2 register. it is cleared by a software se- quence (an access to the sr register followed by a write to the dr register). 0: transmission is not complete 1: transmission is complete bit 5 = rdrf received data ready flag. this bit is set by hardware when the content of the rdr register has been transferred into the dr register. an interrupt is generated if rie=1 in the cr2 register. it is cleared by hardware when re=0 or by a software sequence (an access to the sr register followed by a read to the dr register). 0: data is not received 1: received data is ready to be read bit 4 = idle idle line detect. this bit is set by hardware when a idle line is de- tected. an interrupt is generated if the ilie=1 in the cr2 register. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rdrf bit has been set itself (i.e. a new idle line oc- curs). this bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. bit 3 = or overrun error. this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rdrf=1. an interrupt is generated if rie=1 in the cr2 reg- ister. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set rdr register content will not be lost but the shift register will be overwritten. bit 2 = nf noise flag. this bit is set by hardware when noise is detected on a received frame. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr regis- ter). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. bit 1 = fe framing error. this bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. it is cleared by hardware when re=0 by a software sequence (an access to the sr register followed by a read to the dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it ap- pears at the same time as the rdrf bit which it- self generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the or bit will be set. bit 0 = unused. 70 tdre tc rdrf idle or nf fe -
st72311r, st72511r, st72512r, st72532r 101/164 serial communications interface (cont'd) control register 1 (cr1) read/write reset value: undefined bit 7 = r8 receive data bit 8. this bit is used to store the 9th bit of the received word when m=1. bit 6 = t8 transmit data bit 8. this bit is used to store the 9th bit of the transmit- ted word when m=1. bit 4 = m word length. this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, 1 stop bit 1: 1 start bit, 9 data bits, 1 stop bit bit 3 = wake wake-up method. this bit determines the sci wake-up method, it is set or cleared by software. 0: idle line 1: address mark control register 2 (cr2) read/write reset value: 0000 0000 (00h) bit 7 = tie transmitter interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tdre=1 in the sr register. bit 6 = tcie transmission complete interrupt ena- ble this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever tc=1 in the sr register bit 5 = rie receiver interrupt enable . this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever or=1 or rdrf=1 in the sr register bit 4 = ilie idle line interrupt enable. this bit is set and cleared by software. 0: interrupt is inhibited 1: an sci interrupt is generated whenever idle=1 in the sr register. bit 3 = te transmitter enable. this bit enables the transmitter and assigns the tdo pin to the alternate function. it is set and cleared by software. 0: transmitter is disabled, the tdo pin is back to the i/o port configuration. 1: transmitter is enabled note: during transmission, a a0o pulse on the te bit (a0o followed by a1o) sends a preamble after the current word. bit 2 = re receiver enable. this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled, it resets the rdrf, idle, or, nf and fe bits of the sr register. 1: receiver is enabled and begins searching for a start bit. bit 1 = rwu receiver wake-up. this bit determines if the sci is in mute mode or not. it is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: receiver in active mode 1: receiver in mute mode bit 0 = sbk send break. this bit set is used to send break characters. it is set and cleared by software. 0: no break character is transmitted 1: break characters are transmitted note: if the sbk bit is set to a1o and then to a0o, the transmitter will send a break word at the end of the current word. 70 r8 t8 - m wak e - - - 70 tie tcie rie ilie te re rwu sbk
st72311r, st72511r, st72512r, st72532r 102/164 serial communications interface (cont'd) data register (dr) read/write reset value: undefined contains the received or transmitted data char- acter, depending on whether it is read from or writ- ten to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr). the tdr register provides the parallel interface between the internal bus and the output shift reg- ister (see figure 52). the rdr register provides the parallel interface between the input shift register and the internal bus (see figure 52). baud rate register (brr) read/write reset value: 00xx xxxx (xxh) bit 7:6= scp[1:0] first sci prescaler these 2 prescaling bits allow several standard clock division ranges: bit 5:3 = sct[2:0] sci transmitter rate divisor these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al baud rate generator mode. note: this tr factor is used only when the etpr fine tuning factor is equal to 00h; otherwise, tr is replaced by the etpr dividing factor. bit 2:0 = scr[2:0] sci receiver rate divisor. these 3 bits, in conjunction with the scp1 & scp0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional baud rate generator mode. note: this rr factor is used only when the erpr fine tuning factor is equal to 00h; otherwise, rr is replaced by the erpr dividing factor. 70 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 70 scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 pr prescaling factor scp1 scp0 100 301 410 13 1 1 tr dividi ng factor sct2 sct1 sct0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1 rr dividi ng factor scr2 scr1 scr0 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 1 1 1
st72311r, st72511r, st72512r, st72532r 103/164 serial communications interface (cont'd) extended receive prescaler division register (erpr) read/write reset value: 0000 0000 (00h) allows setting of the extended prescaler rate divi- sion factor for the receive circuit. bit 7:1 = erpr[7:0] 8-bit extended receive pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 54) is divided by the binary factor set in the erpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. extended transmit prescaler division register (etpr) read/write reset value:0000 0000 (00h) allows setting of the external prescaler rate divi- sion factor for the transmit circuit. bit 7:1 = etpr[7:0] 8-bit extended transmit pres- caler register. the extended baud rate generator is activated when a value different from 00h is stored in this register. therefore the clock frequency issued from the 16 divider (see figure 54) is divided by the binary factor set in the etpr register (in the range 1 to 255). the extended baud rate generator is not used af- ter a reset. table 22. sci register map and reset values 70 erpr 7 erpr 6 erpr 5 erpr 4 erpr 3 erpr 2 erpr 1 erpr 0 70 etpr 7 etpr 6 etpr 5 etpr 4 etpr 3 etpr 2 etpr 1 etpr 0 address (hex.) register label 76543210 0050h scisr reset value tdre 1 tc 1 rdrf 0 idle 0 or 0 nf 0 fe 00 0051h scidr reset value msb xxxxxxx lsb x 0052h scibrr reset value scp1 0 scp0 0 sct2 0 sct1 0 sct0 0 scr2 0 scr1 0 scr0 0 0053h scicr1 reset value r8 x t8 x0 m x wake x000 0054h scicr2 reset value tie 0 tcie 0 rie 0 ilie 0 te 0 re 0 rwu 0 sbk 0 0055h scierpr reset value msb 0000000 lsb 0 0057h scietpr reset value msb 0000000 lsb 0
st72311r, st72511r, st72512r, st72532r 104/164 10.7 controller area network (can) 10.7.1 introduction this peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in can specification rev. 2.0 part a. it can also be connected to a 2.0 b network without problems, since extended frames are checked for correctness and acknowledged accordingly although such frames cannot be trans- mitted nor received. the same applies to overload frames which are recognized but never initiated. figure 55. can block diagram tx/rx buffer 1 10 bytes tx/rx buffer 2 10 bytes tx/rx buffer 3 10 bytes id filter 0 4 bytes id filter 1 4 bytes st7 interface psr icr isr brpr csr tecr recr can 2.0b passive core shreg bcdl crc btl rx tx eml st7 internal bus btr
st72311r, st72511r, st72512r, st72532r 105/164 controller area network (cont'd) 10.7.2 main features support of can specification 2.0a and 2.0b pas- sive three prioritized 10-byte transmit/receive mes- sage buffers two programmable global 12-bit message ac- ceptance filters programmable baud rates up to 1 mbit/s buffer flip-flopping capability in transmission maskable interrupts for transmit, receive (one per buffer), error and wake-up automatic low-power mode after 20 recessive bits or on demand (standby mode) interrupt-driven wake-up from standby mode upon reception of dominant pulse optional dominant pulse transmission on leaving standby mode automatic message queuing for transmission upon writing of data byte 7 programmable loop-back mode for self-test op- eration advanced error detection and diagnosis func- tions software-efficient buffer mapping at a unique ad- dress space scalable architecture. 10.7.3 functional description 10.7.3.1 frame formats a summary of all the can frame formats is given in figure 56 for reference. it covers only the stand- ard frame format since the extended one is only acknowledged. a message begins with a start bit called start of frame (sof). this bit is followed by the arbitration field which contains the 11-bit identifier (id) and the remote transmission request bit (rtr). the rtr bit indicates whether it is a data frame or a re- mote request frame. a remote request frame does not have any data byte. the control field contains the identifier extension bit (ide), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (dlc). the data field ranges from zero to eight bytes and is followed by the cyclic redundancy check (crc) used as a frame integrity check for detecting bit errors. the acknowledgement (ack) field comprises the ack slot and the ack delimiter. the bit in the ack slot is placed on the bus by the transmitter as a re- cessive bit (logical 1). it is overwritten as a domi- nant bit (logical 0) by those receivers which have at this time received the data correctly. in this way, the transmitting node can be assured that at least one receiver has correctly received its message. note that messages are acknowledged by the re- ceivers regardless of the outcome of the accept- ance test. the end of the message is indicated by the end of frame (eof). the intermission field defines the minimum number of bit periods separating con- secutive messages. if there is no subsequent bus access by any station, the bus remains idle. 10.7.3.2 hardware blocks the can controller contains the following func- tional blocks (refer to figure 55): st7 interface: buffering of the st7 internal bus and address decoding of the can registers. tx/rx buffers: three 10-byte buffers for trans- mission and reception of maximum length mes- sages. id filters: two 12-bit compare and don't care masks for message acceptance filtering. psr: page selection register (see memory map). brpr: clock divider for different data rates. btr: bit timing register. icr: interrupt control register. isr: interrupt status register. csr: general purpose control/status register. tecr: transmit error counter register. recr: receive error counter register. btl: bit timing logic providing programmable bit sampling and bit clock generation for synchroni- zation of the controller. bcdl: bit coding logic generating a nrz-coded datastream with stuff bits. shreg: 8-bit shift register for serialization of data to be transmitted and parallelisation of re- ceived data. crc: 15-bit crc calculator and checker. eml: error detection and management logic. can core: can 2.0b passive protocol control- ler.
st72311r, st72511r, st72512r, st72532r 106/164 controller area network (cont'd) figure 56. can frames data field 8*n control field 6 arbitration field 12 crc field 16 ack field 7 sof id dlc crc data frame 44 + 8 * n arbitration field 12 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc control field 6 overload flag 6 overload delimiter 8 overload frame error flag 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame data frame or remote frame notes: ? 0 <= n <= 8 ? sof = start of frame ? id = identifier ? rtr = remote transmission request ? ide = identifier extension bit ? r0 = reserved bit ? dlc = data length code ? crc = cyclic redundancy code ? error flag: 6 dominant bits if node is error active else 6 recessive bits. ? suspend transmission: applies to error passive nodes only. ? eof = end of frame ? ack = acknowledge bit data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field end of frame rtr ide r0 eof
st72311r, st72511r, st72512r, st72532r 107/164 controller area network (cont'd) 10.7.3.3 modes of operation the can core unit assumes one of the seven states described below: standby . standby mode is entered either on a chip reset or on resetting the run bit in the con- trol/status register (csr). any on-going trans- mission or reception operation is not interrupted and completes normally before the bit time log- ic and the clock prescaler are turned off for mini- mum power consumption. this state is signalled by the run bit being read-back as 0. once in standby, the only event monitored is the reception of a dominant bit which causes a wake- up interrupt if the scie bit of the interrupt control register (icr) is set. the standby mode is left by setting the run bit. if the wkps bit is set in the csr register, then the controller passes through wake-up otherwise it enters resync directly. it is important to note that the wake-up mecha- nism is software-driven and therefore carries a significant time overhead. all messages received after the wake-up bit and before the controller is set to run and has completed synchronization are ignored. wake-up . the can bus line is forced to domi- nant for one bit time signalling the wake-up con- dition to all other bus members. figure 57. can controller state diagram n stan dby resync wake-up recepti on transmis sion error idle areset run run & wkps run & wkp s fsyn & boff & 11 recessive bits | (fsyn | boff ) & 128 * 11 recessive bits run write to data7 | tx error & nrtx start of frame arbitration lost tx error rx error tx ok rx ok boff boff
st72311r, st72511r, st72512r, st72532r 108/164 controller area network (cont'd) resync . the resynchronization mode is used to find the correct entry point for starting trans- mission or reception after the node has gone asynchronous either by going into the standby or bus-off states. resynchronization is achieved when 128 se- quences of 11 recessive bits have been moni- tored unless the node is not bus-off and the fsyn bit in the csr register is set in which case a single sequence of 11 recessive bits needs to be monitored. idle . the can controller looks for one of the fol- lowing events: the run bit is reset, a start of frame appears on the can bus or the data7 register of the currently active page is written to. transmission . once the lock bit of a buffer control/status register (bcsrx) has been set and read back as such, a transmit job can be submitted by writing to the data7 register. the message with the highest priority will be transmit- ted as soon as the can bus becomes idle. among those messages with a pending trans- mission request, the highest priority is given to buffer 3 then 2 and 1. if the transmission fails due to a lost arbitration or to an error while the nrtx bit of the csr register is reset, then a new trans- mission attempt is performed . this goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by set- ting the nrtx bit or if the node ever enters bus- off or if a higher priority message becomes pend- ing. the rdy bit in the bcsrx register, which was set since the job was submitted, gets reset. when a transmission is in progress, the busy bit in the bcsrx register is set. if it ends successful- ly then the txif bit in the interrupt status regis- ter (isr) is set, else the teif bit is set. an interrupt is generated in either case provided the txie and teie bits of the icr register are set. the etx bit in the same register is used to get an early transmit interrupt and to automatically un- lock the transmitting buffer upon successful com- pletion of its job. this enables the cpu to get a new transmit job pending by the end of the cur- rent transmission while always leaving two buff- ers available for reception. an uninterrupted stream of messages may be transmitted in this way at no overrun risk. note 1: setting the srte bit of the csr register allows transmitted messages to be simultane- ously received when they pass the acceptance filtering. this is particularly useful for checking the integrity of the communication path. note 2: when the etx bit is reset, the buffer with the highest priority and with a pending transmis- sion request is always transmitted. when the etx bit is set, once a buffer participates in the ar- bitration phase, it is sent until it wins the arbitra- tion even if another transmission is requested from a buffer with a higher priority. reception . once the can controller has syn- chronized itself onto the bus activity, it is ready for reception of new messages. every incoming message gets its identifier compared to the ac- ceptance filters. if the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and a target buffer is searched for. this buffer will be the first one - order is 1 to 3 - that has the lock and rdy bits of its bcsrx regis- ter reset. when no such buffer exists then an overrun interrupt is generated if the orie bit of the icr register has been set. in this case the identifi- er of the last message is made available in the last identifier register (lidhr and lidlr) at least until it gets overwritten by a new identifi- er picked-up from the bus. when a buffer does exist, the accepted mes- sage gets written into it, the acc bit in the bcsrx register gets the number of the match- ing filter, the rdy and rxif bits get set and an interrupt is generated if the rxie bit in the isr register is set. up to three messages can be automatically received without intervention from the cpu because each buffer has its own set of status bits, greatly reducing the reactiveness require- ments in the processing of the receive inter- rupts.
st72311r, st72511r, st72512r, st72532r 109/164 controller area network (cont'd) error . the error management as described in the can protocol is completely handled by hard- ware using 2 error counters which get increment- ed or decremented according to the error condition. both of them may be read by the appli- cation to determine the stability of the network. moreover, as one of the node status bits (epsv or boff of the csr register) changes, an inter- rupt is generated if the scie bit is set in the icr register. refer to figure 58. figure 58. can error state diagram error passi ve when tecr or recr > 127, the epsv bit gets set when tecr and recr < 128, and the epsv bit gets cleared error acti ve bus off when tecr > 255 the boff bit gets set when 128 * 11 recessive bits occur: - the boff bit gets cleared - the tecr register gets cleared - the recr register gets cleared the epsv bit gets cleared
st72311r, st72511r, st72512r, st72532r 110/164 controller area network (cont'd) 10.7.3.4 bit timing logic the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronizing on following edges. its operation may be explained simply when the nominal bit time is divided into three segments as follows: synchronisation segment (sync_seg) : a bit change is expected to lie within this time seg- ment. it has a fixed length of one time quanta (1 xt can ). bit segment 1 (bs1) : defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can standard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compen- sate for positive phase drifts due to differences in the frequency of the various nodes of the net- work. bit segment 2 (bs2) : defines the location of the transmit point. it represents the phase_seg2 of the can standard. its duration is programma- ble between 1 and 8 time quanta but may also be automatically shortened to compensate for neg- ative phase drifts. the resynchronization jump width (rjw) defines an upper bound to the amount of lengthening or shortening of the bit segments. it is programmable between 1 and 4 time quanta. a valid edge is defined as the first transition in a bit time from dominant to recessive bus level provid- ed the controller itself does not send a recessive bit. if a valid edge is detected in bs1 instead of sync_seg, bs1 is extended by up to rjw so that the sample point is delayed. conversely, if a valid edge is detected in bs2 in- stead of sync_seg, bs2 is shortened by up to rjw so that the transmit point is moved earlier. as a safeguard against programming errors, the configuration of the bit timing register (btr) is only possible while the device is in standby mode. figure 59. bit timing sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1xt can t bs1 t bs2 sample point trans mit point
st72311r, st72511r, st72512r, st72532r 111/164 controller area network (cont'd) 10.7.4 register description the can registers are organized as 6 general pur- pose registers plus 5 pages of 16 registers span- ning the same address space and primarily used for message and filter storage. the page actually selected is defined by the content of the page se- lection register. refer to figure 60. 10.7.4.1 general purpose registers interrupt status register (isr) read/write reset value: 00h bit 7 = rxif3 receive interrupt flag for buffer 3 - read/clear set by hardware to signal that a new error-free mes- sage is available in buffer 3. cleared by software to release buffer 3. also cleared by resetting bit rdy of bcsr3. bit 6 = rxif2 receive interrupt flag for buffer 2 - read/clear set by hardware to signal that a new error-free message is available in buffer 2. cleared by software to release buffer 2. also cleared by resetting bit rdy of bcsr2. bit 5 = rxif1 receive interrupt flag for buffer 1 - read/clear set by hardware to signal that a new error-free mes- sage is available in buffer 1. cleared by software to release buffer 1. also cleared by resetting bit rdy of bcsr1. bit 4 = txif transmit interrupt flag - read/clear set by hardware to signal that the highest priority message queued for transmission has been suc- cessfully transmitted (etx = 0) or that it has passed successfully the arbitration (etx = 1). cleared by software. bit 3 = scif status change interrupt flag - read/clear set by hardware to signal the reception of a domi- nant bit while in standby or a change from error ac- tive to error passive and bus-off while in run. also signals any receive error when esci = 1. cleared by software. bit 2 = orif overrun interrupt flag - read/clear set by hardware to signal that a message could not be stored because no receive buffer was available. cleared by software. bit 1 = teif transmit error interrupt flag - read/clear set by hardware to signal that an error occurred dur- ing the transmission of the highest priority message queued for transmission. cleared by software. bit 0 = epnd error interrupt pending - read only set by hardware when at least one of the three error interrupt flags scif, orif or teif is set. reset by hardware when all error interrupt flags have been cleared. caution ; interrupt flags are reset by writing a o0o to the cor- responding bit position. the appropriate way con- sists in writing an immediate mask or the one's com- plement of the register content initially read by the interrupt handler. bit manipulation instruction bres should never be used due to its read-modify- write nature. 70 rxif3 rxif2 rxif1 txif scif orif teif epnd
st72311r, st72511r, st72512r, st72532r 112/164 controller area network (cont'd) interrupt control register (icr) read/write reset value: 00h bit 6 = esci extended status change interrupt - read/set/clear set by software to specify that scif is to be set on receive errors also. cleared by software to set scif only on status changes and wake-up but not on all receive errors. bit 5 = rxie receive interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message has been received free of er- rors. cleared by software to disable receive interrupt re- quests. bit 4 = txie transmit interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message has been successfully trans- mitted. cleared by software to disable transmit interrupt requests. bit 3 = scie status change interrupt enable - read/set/clear set by software to enable an interrupt request whenever the node's status changes in run mode or whenever a dominant pulse is received in standby mode. cleared by software to disable status change inter- rupt requests. bit 2 = orie overrun interrupt enable - read/set/clear set by software to enable an interrupt request whenever a message should be stored and no re- ceive buffer is avalaible. cleared by software to disable overrun interrupt re- quests. bit 1 = teie transmit error interrupt enable - read/set/clear set by software to enable an interrupt whenever an error has been detected during transmission of a message. cleared by software to disable transmit error inter- rupts. bit 0 = etx early transmit interrupt - read/set/clear set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully. cleared by software to request the transmit inter- rupt to occur at the completion of the transfer. 70 0 esci rxie txie scie orie teie etx
st72311r, st72511r, st72512r, st72532r 113/164 controller area network (cont'd) control/status register (csr) read/write reset value: 00h bit 6 = boff bus-off state - read only set by hardware to indicate that the node is in bus- off state, i.e. the transmit error counter exceeds 255. reset by hardware to indicate that the node is in- volved in bus activities. bit 5 = epsv error passive state - read only set by hardware to indicate that the node is error passive. reset by hardware to indicate that the node is either error active (boff = 0) or bus-off. bit 4 = srte simultaneous receive/transmit en- able - read/set/clear set by software to enable simultaneous transmis- sion and reception of a message passing the ac- ceptance filtering. allows to check the integrity of the communication path. reset by software to discard all messages trans- mitted by the node. allows remote and data frames to share the same identifier. bit 3 = nrtx no retransmission - read/set/clear set by software to disable the retransmission of un- successful messages. cleared by software to enable retransmission of messages until success is met. bit 2 = fsyn fast synchronization - read/set/clear set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 re- cessive bits in a row. cleared by software to enable the standard resyn- chronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits. bit 1 = wkps wake-up pulse - read/set/clear set by software to generate a dominant pulse when leaving standby mode. cleared by software for no dominant wake-up pulse. bit 0 = run can enable - read/set/clear set by software to leave standby mode after 128 se- quences of 11 recessive bits or just 11 recessive bits if fsyn is set. cleared by software to request a switch to the standby or low-power mode as soon as any on-go- ing transfer is complete. read-back as 1 in the meantime to enable proper signalling of the standby state. the cpu clock may therefore be safely switched off whenever run is read as 0. 70 0 boff epsv srte nrtx fsyn wkps run
st72311r, st72511r, st72512r, st72532r 114/164 controller area network (cont'd) baud rate prescaler register (brpr) read/write in standby mode reset value: 00h rjw[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization. t rjw =t can * (rjw + 1) brp[5:0] determine the can system clock cycle time or time quanta which is used to build up the in- dividual bit timing. t can =t cpu * (brp + 1) where t cpu = time period of the cpu clock. the resulting baud rate can be computed by the for- mula: note: writing to this register is allowed only in standby mode to prevent any accidental can pro- tocol violation through programming errors. bit timing register (btr) read/write in standby mode reset value: 23h bs2[2:0] determine the length of bit segment 2. t bs2 =t can * (bs2 + 1) bs1[3:0] determine the length of bit segment 1. t bs1 =t can * (bs1 + 1) note: writing to this register is allowed only in standby mode to prevent any accidental can pro- tocol violation through programming errors. page selection register (psr) read/write reset value: 00h page[2:0] determine which buffer or filter page is mapped at addresses 0010h to 001fh. 70 rjw1 rjw0 brp5 brp4 brp3 brp2 brp1 brp0 br 1 t cpu brp 1 + () bs 1 bs 23 ++ () --------------------------------------------------------------------------------------------- - = 70 0 bs22 bs21 bs20 bs13 bs12 bs11 bs10 70 00000 page 2 page 1 page 0 page2 page1 page0 page title 0 0 0 diagnosis 0 0 1 buffer 1 0 1 0 buffer 2 0 1 1 buffer 3 1 0 0 filters 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
st72311r, st72511r, st72512r, st72532r 115/164 controller area network (cont'd) 10.7.4.2 paged registers last identifier high register (lidhr) read/write reset value: undefined lid[10:3] are the most significant 8 bits of the last identifier read on the can bus. last identifier low register (lidlr) read/write reset value: undefined lid[2:0] are the least significant 3 bits of the last identifier read on the can bus. lrtr is the last remote transmission request bit read on the can bus. ldlc[3:0] is the last data length code read on the can bus. transmit error counter reg. (tecr) read only reset value: 00h tec[7:0] is the least significant byte of the 9-bit transmit error counter implementing part of the fault confinement mechanism of the can protocol. in case of an error during transmission, this counter is incremented by 8. it is decremented by 1 after every successful transmission. when the counter value exceeds 127, the can controller enters the error passive state. when a value of 256 is reached, the can controller is disconnected from the bus. receive error counter reg. (recr) page: 00h e read only reset value: 00h rec[7:0] is the receive error counter implement- ing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can stand- ard. after every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. identifier high registers (idhrx) read/write reset value: undefined id[10:3] are the most significant 8 bits of the 11-bit message identifier.the identifier acts as the mes- sage's name, used for bus access arbitration and acceptance filtering. 70 lid10 lid9 lid8 lid7 lid6 lid5 lid4 lid3 70 lid2 lid1 lid0 lrtr ldlc 3 ldlc 2 ldlc 1 ldlc 0 70 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 70 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 70 id10 id9 id8 id7 id6 id5 id4 id3
st72311r, st72511r, st72512r, st72532r 116/164 controller area network (cont'd) identifier low registers (idlrx) read/write reset value: undefined id[2:0] are the least significant 3 bits of the 11-bit message identifier. rtr is the remote transmission request bit. it is set to indicate a remote frame and reset to indicate a data frame. dlc[3:0] is the data length code. it gives the number of bytes in the data field of the mes- sage.the valid range is 0 to 8. data registers (data0-7x) read/write reset value: undefined data[7:0] is amessage data byte. upto eight such bytes may be part of a message. writing to byte data7 initiates a transmit request and should al- ways be done even when data7 is not part of the message. buffer control/status regs. (bcsrx) read/write reset value: 00h bit 3 = acc acceptance code - read only set by hardware with the id of the highest priority filter which accepted the message stored in the buffer. acc = 0: match for filter/mask0. possible match for filter/mask1. acc = 1: no match for filter/mask0 and match for filter/mask1. reset by hardware when either rdy or rxif gets reset. bit 2 = rdy message ready - read/clear set by hardware to signal that a new error-free message is available (lock = 0) or that a trans- mission request is pending (lock = 1). cleared by software when lock = 0 to release the buffer and to clear the corresponding rxif bit in the interrupt status register. cleared by hardware when lock = 1 to indicate that the transmission request has been serviced or cancelled. bit 1 = busy busy buffer - read only set by hardware when the buffer is being filled (lock = 0) or emptied (lock = 1). reset by hardware when the buffer is not ac- cessed by the can core for transmission nor re- ception purposes. bit 0 = lock lock buffer - read/set/clear set by software to lock a buffer. no more message can be received into the buffer thus preserving its content and making it available for transmission. cleared by software to make the buffer available for reception. cancels any pending transmission request. cleared by hardware once a message has been successfully transmitted provided the early trans- mit interrupt mode is on. left untouched otherwise. note that in order to prevent any message corrup- tion or loss of context, lock cannot be set nor re- set while busy is set. trying to do so will result in lock not changing state. 70 id2 id1 id0 rtr dlc3 dlc2 dlc1 dlc0 70 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 70 0 0 0 0 acc rdy busy lock
st72311r, st72511r, st72512r, st72532r 117/164 controller area network (cont'd) filter high registers (fhrx) read/write reset value: undefined fil[11:3] are the most significant 8 bits of a 12-bit message filter. the acceptance filter is compared bit by bit with the identifier and the rtr bit of the incoming message. if there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. filter low registers (flrx) read/write reset value: undefined fil[3:0] are the least significant 4 bits of a 12-bit message filter. mask high registers (mhrx) read/write reset value: undefined msk[11:3] are the most significant 8 bits of a 12- bit message mask. the acceptance mask defines which bits of the acceptance filter should match the identifier and the rtr bit of the incoming mes- sage. msk i = 0: don't care. msk i = 1: match required. mask low registers (mlrx) read/write reset value: undefined msk[3:0] are the least significant 4 bits of a 12-bit message mask. 70 fil11 fil10 fil9 fil8 fil7 fil6 fil5 fll4 70 fil3 fil2 fil1 fil0 0 0 0 0 70 msk1 1 msk1 0 msk9 msk8 msk7 msk6 msk5 msk4 70 msk3 msk2 msk1 msk0 0 0 0 0
st72311r, st72511r, st72512r, st72532r 118/164 controller area network (cont'd) figure 60. can register map interrupt status interrupt control control/status baud rate prescaler page selection paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 paged reg0 paged reg1 paged reg2 paged reg3 paged reg4 paged reg5 paged reg6 paged reg7 paged reg8 paged reg9 paged reg10 paged reg11 paged reg12 paged reg13 paged reg14 paged reg15 6fh 5ch 5ah 5bh 5dh 5fh 60h bit timing 5eh
st72311r, st72511r, st72512r, st72532r 119/164 controller area network (cont'd) figure 61. page maps 60 h 61 h 62 h 63 h 64 h 65 h 66 h 67 h 68 h 69 h 6a h 6b h 6ch 6dh 6e h 6fh fhr0 flr0 mhr0 mlr0 fhr1 flr1 mhr1 mlr1 reserved idhr1 idlr1 data 01 data 11 data 21 data 31 data 41 data 51 data 61 data 71 reserved bcsr1 lidhr lidlr reserved tstr tecr recr idhr2 idlr2 data02 data12 data22 data32 data42 data52 data62 data72 reserved bcsr2 idhr3 idlr3 data03 data13 data23 data33 data43 data53 data63 data73 reserved bcsr3 page 0 page 1 page 2 page 3 page 4 diagnosis buffer 1 buffer 2 buffer 3 acceptance filters
st72311r, st72511r, st72512r, st72532r 120/164 controller area network (cont'd) table 23. can register map and reset values address (hex.) page register label 7 6 543210 5a canisr reset value rxif3 0 rxif2 0 rxif1 0 txif 0 scif 0 orif 0 teif 0 epnd 0 5b canicr reset value 0 esci 0 rxie 0 txie 0 scie 0 orie 0 teie 0 etx 0 5c cancsr reset value 0 boff 0 epsv 0 srte 0 nrtx 0 fsyn 0 wkps 0 run 0 5d canbrpr reset value rjw1 0 rjw0 0 brp5 0 brp4 0 brp3 0 brp2 0 brp1 0 brp0 0 5e canbtr reset value 0 bs22 0 bs21 1 bs20 0 bs13 0 bs12 0 bs11 1 bs10 1 5f canpsr reset value 0 0 0 0 0 page2 0 page1 0 page0 0 60 0 canlidhr reset value lid10 x lid9 x lid8 x lid7 x lid6 x lid5 x lid4 x lid3 x 1to3 canidhrx reset value id10 x id9 x id8 x id7 x id6 x id5 x id4 x id3 x 60, 64 4 canfhrx reset value fil11 x fil10 x fil9 x fil8 x fil7 x fil6 x fil5 x fil4 x 61 0 canlidlr reset value lid2 x lid1 x lid0 x lrtr x ldlc3 x ldlc2 x ldlc1 x ldlc0 x 1to3 canidlrx reset value id2 x id1 x id0 x rtr x dlc3 x dlc2 x dlc1 x dlc0 x 61, 65 4 canflrx reset value fil3 x fil2 x fil1 x fil0 x00 0 0 62 to 69 1 to 3 candrx reset value msb xxxxxxx lsb x 62, 66 4 canmhrx reset value msk11 x msk10 x msk9 x msk8 x msk7 x msk6 x msk5 x msk4 x 63, 67 4 canmlrx reset value msk3 x msk2 x msk1 x msk0 x00 0 0 6e 0 cantecr reset value msb 0000000 lsb 0 6f canrecr reset value msb 0000000 lsb 0 1to3 canbcsrx reset value 0 0 0 0 acc 0 rdy 0 busy 0 lock 0
st72311r, st72511r, st72512r, st72532r 121/164 10.8 8-bit a/d converter (adc) 10.8.1 introduction the on-chip analog to digital converter (adc) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. this peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. 10.8.2 main features n 8-bit conversion n up to 16 channels with multiplexed input n linear successive approximation n data register (dr) which contains the results n conversion complete status flag n on/off bit (to reduce consumption) the block diagram is shown in figure 62. 10.8.3 functional description 10.8.3.1 analog power supply v dda and v ssa are the high and low level refer- ence voltage pins. in some devices (refer to device pin out description) they are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. see electrical characteristics section for more de- tails. figure 62. adc block diagram ch2 ch1 ch3 coco 0 adon 0 ch0 adccsr ain0 ain1 analog to digital converter ainx analog mux r adc c adc d2 d1 d3 d7 d6 d5 d4 d0 adcdr 4 div 2 f adc f cpu hold control
st72311r, st72511r, st72512r, st72532r 122/164 8-bit a/d converter (adc) (cont'd) 10.8.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con- version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adcdr register. the accuracy of the conversion is described in the parametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 10.8.3.3 a/d conversion phases the a/d conversion is based on two conversion phases as shown in figure 63: n sample capacitor loading [duration: t load ] during this phase, the v ain input voltage to be measured is loaded into the c adc sample capacitor. n a/d conversion [duration: t conv ] during this phase, the a/d conversion is computed (8 successive approximations cycles) and the c adc sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. while the adc is on, these two phases are contin- uously repeated. at the end of each conversion, the sample capaci- tor is kept loaded with the previous measurement load. the advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement. 10.8.3.4 software procedure refer to the control/status register (csr) and data register (dr) in section 10.8.6 for the bit defini- tions and to figure 63 for the timings. adc configuration the total duration of the a/d conversion is 12 adc clock periods (1/f adc =2/f cpu ). the analog input ports must be configured as in- put, no pull-up, no interrupt. refer to the ?i/o ports? chapter. using these pins as analog inputs does not affect the ability of the port to be read as a logic input. in the csr register: select the ch[3:0] bits to assign the analog channel to be converted. adc conversion in the csr register: set the adon bit to enable the a/d converter and to start the first conversion. from this time on, the adc performs a continuous conver- sion of the selected channel. when a conversion is complete the coco bit is set by hardware. no interrupt is generated. the result is in the dr register and remains valid until the next conversion has ended. a write to the csr register (with adon set) aborts the current conversion, resets the coco bit and starts a new conversion. figure 63. adc conversion timings 10.8.4 low power modes note : the a/d converter may be disabled by reset- ting the adon bit. this feature allows reduced power consumption when no conversion is needed and between single shot conversions. 10.8.5 interrupts none mode description wait no effect on a/d converter halt a/d converter disabled. after wakeup from halt mode, the a/d con- verter requires a stabilisation time before ac- curate conversions can be performed. adccsr write adon coco bit set t load t conv operation hold control
st72311r, st72511r, st72512r, st72532r 123/164 8-bit a/d converter (adc) (cont'd) 10.8.6 register description control/status register (csr) read/write reset value: 0000 0000 (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by soft- ware reading the result in the dr register or writing to the csr register. 0: conversion is not complete 1: conversion can be read from the dr register bit 6 = reserved. must always be cleared. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off 1: a/d converter is switched on bit 4 = reserved. must always be cleared. bit 3:0 = ch[3:0] channel selection these bits are set and cleared by software. they select the analog input to convert. *note : the number of pins and the channel selec- tion varies according to the device. refer to the de- vice pinout. data register (dr) read only reset value: 0000 0000 (00h) bit 7:0 = d[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. note : reading this register reset the coco flag. 70 coco 0 adon 0 ch3 ch2 ch1 ch0 channel pin* ch3 ch2 ch1 ch0 ain0 0 0 0 0 ain1 0 0 0 1 ain2 0 0 1 0 ain3 0 0 1 1 ain4 0 1 0 0 ain5 0 1 0 1 ain6 0 1 1 0 ain7 0 1 1 1 ain8 1 0 0 0 ain9 1 0 0 1 ain10 1 0 1 0 ain11 1 0 1 1 ain12 1 1 0 0 ain13 1 1 0 1 ain14 1 1 1 0 ain15 1 1 1 1 70 d7 d6 d5 d4 d3 d2 d1 d0
st72311r, st72511r, st72512r, st72532r 124/164 8-bit a/d convertor (adc) (cont'd) table 24. adc register map and reset values address (hex.) register label 76543210 0070h adcdr reset value d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 0 0071h adccsr standard reset value coco 0 adon 00 ch2 ch1 ch0 00 000
st72311r, st72511r, st72512r, st72532r 125/164 11 instruction set 11.1 st7 addressing modes the st7 core features 17 different addressing modes which can be classified in 7 main groups: the st7 instruction set is designed to minimize the number of bytes required per instruction: to do so, most of the addressing modes may be subdi- vided in two sub-modes called long and short: long addressing mode is more powerful be- cause it can use the full 64 kbyte address space, however it uses more bytes and more cpu cy- cles. short addressing mode is less powerful because it can generally only access page zero (0000h - 00ffh range), but the instruction size is more compact, and faster. all memory to memory in- structions use short addressing modes only (clr, cpl, neg, bset, bres, btjt, btjf, inc, dec, rlc, rrc, sll, srl, sra, swap) the st7 assembler optimizes the use of long and short addressing modes. table 25. st7 addressing mode overview addressing mode example inherent nop immediate ld a,#$55 direct ld a,$55 indexed ld a,($55,x) indirect ld a,([$55],x) relative jrne loop bit operation bset byte,#5 mode syntax destination pointer address (hex.) pointer size (hex.) length (bytes) inherent nop + 0 immediate ld a,#$55 + 1 short direct ld a,$10 00..ff + 1 long direct ld a,$1000 0000..ffff + 2 no offset direct indexed ld a,(x) 00..ff + 0 short direct indexed ld a,($10,x) 00..1fe + 1 long direct indexed ld a,($1000,x) 0000..ffff + 2 short indirect ld a,[$10] 00..ff 00..ff byte + 2 long indirect ld a,[$10.w] 0000..ffff 00..ff word + 2 short indirect indexed ld a,([$10],x) 00..1fe 00..ff byte + 2 long indirect indexed ld a,([$10.w],x) 0000..ffff 00..ff word + 2 relative direct jrne loop pc+/-127 + 1 relative indirect jrne [$10] pc+/-127 00..ff byte + 2 bit direct bset $10,#7 00..ff + 1 bit indirect bset [$10],#7 00..ff 00..ff byte + 2 bit direct relative btjt $10,#7,skip 00..ff + 2 bit indirect relative btjt [$10],#7,skip 00..ff 00..ff byte + 3
st72311r, st72511r, st72512r, st72532r 126/164 instruction set overview (cont'd) 11.1.1 inherent all inherent instructions consist of a single byte. the opcode fully specifies all the required informa- tion for the cpu to process the operation. 11.1.2 immediate immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value. 11.1.3 direct in direct instructions, the operands are referenced by their memory address. the direct addressing mode consists of two sub- modes: direct (short) the address is a byte, thus requires only one byte after the opcode, but only allows 00 - ff address- ing space. direct (long) the address is a word, thus allowing 64 kbyte ad- dressing space, but requires 2 bytes after the op- code. 11.1.4 indexed (no offset, short, long) in this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (x or y) with an offset. the indirect addressing mode consists of three sub-modes: indexed (no offset) there is no offset, (no extra byte after the opcode), and allows 00 - ff addressing space. indexed (short) the offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1fe addressing space. indexed (long) the offset is a word, thus allowing 64 kbyte ad- dressing space and requires 2 bytes after the op- code. 11.1.5 indirect (short, long) the required data byte to do the operation is found by its memory address, located in memory (point- er). the pointer address follows the opcode. the indi- rect addressing mode consists of two sub-modes: indirect (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - ff addressing space, and requires 1 byte after the opcode. indirect (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. inherent instruction function nop no operation trap s/w interrupt wfi wait for interrupt (low pow- er mode) halt halt oscillator (lowest power mode) ret sub-routine return iret interrupt sub-routine return sim set interrupt mask (level 3) rim reset interrupt mask (level 0) scf set carry flag rcf reset carry flag rsp reset stack pointer ld load clr clear push/pop push/pop to/from the stack inc/dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement mul byte multiplication sll, srl, sra, rlc, rrc shift and rotate operations swap swap nibbles immediate instruction function ld load cp compare bcp bit compare and, or, xor logical operations adc, add, sub, sbc arithmetic operations
st72311r, st72511r, st72512r, st72532r 127/164 instruction set overview (cont'd) 11.1.6 indirect indexed (short, long) this is a combination of indirect and short indexed addressing modes. the operand is referenced by its memory address, which is defined by the un- signed addition of an index register value (x or y) with a pointer value located in memory. the point- er address follows the opcode. the indirect indexed addressing mode consists of two sub-modes: indirect indexed (short) the pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1fe addressing space, and requires 1 byte after the opcode. indirect indexed (long) the pointer address is a byte, the pointer size is a word, thus allowing 64 kbyte addressing space, and requires 1 byte after the opcode. table 26. instructions supporting direct, indexed, indirect and indirect indexed addressing modes 11.1.7 relative mode (direct, indirect) this addressing mode is used to modify the pc register value, by adding an 8-bit signed offset to it. the relative addressing mode consists of two sub- modes: relative (direct) the offset is following the opcode. relative (indirect) the offset is defined in memory, which address follows the opcode. long and short instructions function ld load cp compare and, or, xor logical operations adc, add, sub, sbc arithmetic additions/sub- stractions operations bcp bit compare short instructions only functio n clr clear inc, dec increment/decrement tnz test negative or zero cpl, neg 1 or 2 complement bset, bres bit operations btjt, btjf bit test and jump opera- tions sll, srl, sra, rlc, rrc shift and rotate opera- tions swap swap nibbles call, jp call or jump subroutine available relative direct/indirect instructions function jrxx conditional jump callr call relative
st72311r, st72511r, st72512r, st72532r 128/164 instruction set overview (cont'd) 11.2 instruction groups the st7 family devices use an instruction set consisting of 63 instructions. the instructions may be subdivided into 13 main groups as illustrated in the following table: using a pre-byte the instructions are described with one to four op- codes. in order to extend the number of available op- codes for an 8-bit cpu (256 opcodes), three differ- ent prebyte opcodes are defined. these prebytes modify the meaning of the instruction they pre- cede. the whole instruction becomes: pc-2 end of previous instruction pc-1 prebyte pc opcode pc+1 additional word (0 to 2) according to the number of bytes required to compute the ef- fective address these prebytes enable instruction in y as well as indirect addressing modes to be implemented. they precede the opcode of the instruction in x or the instruction using direct addressing mode. the prebytes are: pdy 90 replace an x based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a y one. pix 92 replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. it also changes an instruction using x indexed ad- dressing mode to an instruction using indirect x in- dexed addressing mode. piy 91 replace an instruction using x in- direct indexed addressing mode by a y one. load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operation bset bres conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf
st72311r, st72511r, st72512r, st72532r 129/164 instruction set overview (cont'd) mnemo description function /example dst src i1 h i0 n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 0 1 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m n z 1 dec decrement dec y reg, m n z halt halt 10 iret interrupt routine return pop cc, a, x, pc i1 h i0 n z c inc increment inc x reg, m n z jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if port b int pin = 1 (no port b interrupts) jril jump if port b int pin = 0 (port b interrupt) jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i1:0 = 11 i1:0 = 11 ? jrnm jump if i1:0 <> 11 i1:0 <> 11 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned >
st72311r, st72511r, st72512r, st72532r 130/164 instruction set overview (cont'd) mnemo description function /example dst src i1 h i0 n z c jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg n z mul multiply x,a = x * a a, x, y x, y, a 0 0 neg negate (2's compl) neg $10 reg, m n z c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m i1 h i0 n z c push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i1:0 = 10 (level 0) 1 0 rlc rotate left true c c <= a <= c reg, m n z c rrc rotate right true c c => a => c reg, m n z c rsp reset stack pointer s = max allowed sbc substract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i1:0 = 11 (level 3) 1 1 sla shift left arithmetic c <= a <= 0 reg, m n z c sll shift left logic c <= a <= 0 reg, m n z c srl shift right logic 0 => a => c reg, m 0 z c sra shift right arithmetic a7 => a => c reg, m n z c sub substraction a = a - m a m n z c swap swap nibbles a7-a4 <=> a3-a0 reg, m n z tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 1 wfi wait for interrupt 1 0 xor exclusive or a = a xor m a m n z
st72311r, st72511r, st72512r, st72532r 131/164 12 electrical characteristics 12.1 parameter conditions unless otherwise specified, all voltages are re- ferred to v ss . 12.1.1 minimum and maximum values unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25 c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the min- imum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 s ). 12.1.2 typical values unless otherwise specified, typical data are based on t a =25 c, v dd =5v (for the 4.5v v dd 5.5v voltage range) and v dd =3.3v (for the 3v v dd 4v voltage range). they are given only as design guidelines and are not tested. 12.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 12.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 64. figure 64. pin loading conditions 12.1.5 pin input voltage the input voltage measurement on a pin of the de- vice is described in figure 65. figure 65. pin input voltage c l st7 pin v in st7 pin
st72311r, st72511r, st72512r, st72532r 132/164 12.2 absolute maximum ratings stresses above those listed as aabsolute maxi- mum ratingso may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device under these condi- tions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 12.2.1 voltage characteristics 12.2.2 current characteristics 12.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuration occurs (for example, due to a corrupted program counter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k w for reset, 10k w for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset configuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st72311r, st72511r, st72512r, st72532r 133/164 12.3 operating conditions 12.3.1 general operating conditions figure 66. f osc maximum operating frequency versus v dd supply for devices without eeprom 2) figure 67. f osc maximum operating frequency versus v dd supply for device with eeprom 2) notes: 1. guaranteed by construction. a/d operation is not guaranteed below 1mhz. 2. operating conditions with t a =-40 to +125 c. symbol parameter conditions min max unit v dd supply voltage see figure 66 and figure 67 3.0 5.5 v f osc external clock frequency v dd 3.5v (without eeprom) v dd 4.5v (with eeprom) 0 1) 16 mhz v dd 3.0v 0 1) 8 t a ambient temperature range 1 suffix version 0 70 c 6 suffix version -40 85 7 suffix version -40 105 3 suffix version -40 125 f osc [mhz] supply voltage [v] 16 8 4 1 0 2.5 3 3.5 4 4.5 5 5.5 functionali ty functi onality functionali ty guarantee d in this area not guaran teed in this area not guaranteed in this area with resona tor 1) f osc [mhz] supply voltage [v] 16 8 4 1 0 2.5 3 3.5 4 4.5 5 5.5 functionali ty funct ionality functionali ty guarantee d in this area not guaran teed in this area not guarantee d in this area with resonato r 1) functionali ty not guaran teed in this area for temperature higher than 85 c
st72311r, st72511r, st72512r, st72532r 134/164 operating conditions (cont'd) 12.3.2 operating conditions with low voltage detector (lvd) subject to general operating condition for v dd ,f osc , and t a . figure 68. lvd threshold versus v dd and f osc for rom devices 2) notes: 1. lvd typical data are based on t a =25 c. they are given only as design guidelines and are not tested. 2. the minimum v dd rise time rate is needed to insure a correct device power-on and lvd reset. not tested in production. symbol parameter condition s min typ 1) max unit v it+ reset release threshold (v dd rise) 3.95 4.15 4.35 v v it- reset generation threshold (v dd fall) 3.70 3.90 4.10 v hyst lvd voltage threshold hysteresis v it+ -v it- 250 mv vt por v dd rise time rate 2) 0.02 v/ms t g(vdd) filtered glitch delay on v dd not detected by the lvd 40 ns f osc [mhz] supply voltage [v] 16 8 0 2.5 3 3.5 4 4.5 5 5.5 functi onal area device under reset in this area functi onality not guaran teed in this area v it- 3.70
st72311r, st72511r, st72512r, st72532r 135/164 12.4 supply current characteristics the following current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode for which the clock is stopped). 12.4.1 run and slow modes figure 69. typical i dd in run vs. f cpu figure 70. typical i dd in slow vs. f cpu notes: 1. typical data are based on t a =25 c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.3v (3v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. cpu running with memory access, all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals switched off; clock input (osc1) driven by external square wave, lvd disabled. 4. slow mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals switched off; clock input (osc1) driven by external square wave, lvd disabled. symbol parameter conditions max unit d i dd( d ta) supply current variation vs. temperature constant v dd and f cpu 10 % symbol parameter conditions typ 1) max 2) unit i dd supply current in run mode 3) (see figure 69) 4.5v v dd 5.5v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 2.5 6.5 14.5 4 9 20 ma supply current in slow mode 4) (see figure 70) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 0.3 0.8 1.8 0.5 2.0 3.0 supply current in run mode 3) (see figure 69) 3v v dd 3.6v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 1.6 3.6 8 2.4 5.4 12 supply current in slow mode 4) (see figure 70) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 0.15 0.45 1 0.3 0.9 1.5 3 3.5 4 4.5 5 5.5 vdd [v] 0 5 10 15 20 idd [ma] 8mhz 4mhz 2mhz 500khz 3 3.5 4 4.5 5 5.5 vdd [v] 0 0.5 1 1.5 2 2.5 idd [ma] 500khz 125khz 31.25khz
st72311r, st72511r, st72512r, st72532r 136/164 supply current characteristics (cont'd) 12.4.2 wait and slow wait modes figure 71. typical i dd in wait vs. f cpu figure 72. typical i dd in slow-wait vs. f cpu notes: 1. typical data are based on t a =25 c, v dd =5v (4.5v v dd 5.5v range) and v dd =3.3v (3v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f cpu max. 3. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals switched off; clock input (osc1) driven by external square wave, lvd disabled. 4. slow-wait mode selected with f cpu based on f osc divided by 32. all i/o pins in input mode with a static value at v dd or v ss (no load), all peripherals switched off; clock input (osc1) driven by external square wave, lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in wait mode 3) (see figure 71) 4.5v v dd 5.5v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 1.25 3.2 5.2 2 5 9 ma supply current in slow wait mode 4) (see figure 72) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 0.2 0.6 1.2 0.35 1 2 supply current in wait mode 3) (see figure 71) 3v v dd 3.6v f osc =1mhz, f cpu =500khz f osc =4mhz, f cpu =2mhz f osc =16mhz, f cpu =8mhz 0.7 1.6 2.7 1 2.6 4.5 supply current in slow wait mode 4) (see figure 72) f osc =1mhz, f cpu =31.25khz f osc =4mhz, f cpu =125khz f osc =16mhz, f cpu =500khz 0.1 0.3 0.6 0.15 0.5 1 3 3.5 4 4.5 5 5.5 vdd [v] 0 1 2 3 4 5 6 7 idd [ma] 8mhz 2mhz 500khz 3 3.5 4 4.5 5 5.5 vdd [v] 0 0.5 1 1.5 idd [ma] 500khz 125khz 31.25khz
st72311r, st72511r, st72512r, st72532r 137/164 supply current characteristics (cont'd) 12.4.3 halt and active-halt modes 12.4.4 supply and clock managers the previous current consumption specified for the st7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. to get the total de- vice consumption, the two current values must be added (except for halt mode). 12.4.5 on-chip peripheral notes: 1. typical data are based on t a =25 c. 2. all i/o pins in input mode with a static value at v dd or v ss (no load), lvd disabled. 3. data based on design simulation and/or technology characteristics, not tested in production. all i/o pins in input mode with a static value at v dd or v ss (no load); clock input (osc1) driven by external square wave, lvd disabled. 4. typical data are based on t a =25 c, v dd =5v. 5. data based on characterization results, not tested in production. 6. data based on characterization results done with the typical external components, not tested in production. 7. as the oscillator is based on a current source, the consumption does not depend on the voltage. 8. data based on a differential i dd measurement between reset configuration (timer counter running at f cpu /4) and timer counter stopped (selecting external clock capability). data valid for one timer. 9. data based on a differential i dd measurement between reset configuration and a permanent spi master communica- tion (data sent equal to 55h). 10. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. symbol parameter conditions typ 1) max unit i dd supply current in halt mode 2) 3.0v v dd v dd 5.5v -40 c t a +105 c 0 10 m a 40 c t a +125 c50 supply current in active-halt mode 3) 50 150 symbol parameter condit ions typ 4) max 5) unit i dd(ck) supply current of resonator oscillator 6) & 7) 600 850 m a i dd(lvd) lvd supply current halt mode 100 150 symbol parameter conditions typ unit i dd(tim) 16-bit timer supply current 8) f cpu =8mhz v dd = 3.3v 50 m a v dd = 5.0v 150 i dd(spi) spi supply current 9) f cpu =8mhz v dd = 3.3v 250 v dd = 5.0v 350 i dd(adc) adc supply current when converting 10) f adc =4mhz v dd = 3.3v 800 v dd = 5.0v 1100
st72311r, st72511r, st72512r, st72532r 138/164 12.5 clock and timing characteristics subject to general operating condition for v dd ,f osc , and t a . 12.5.1 general timings 12.5.2 external clock source figure 73. typical application with an external clock source 12.5.3 crystal and ceramic resonator oscillators notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. d t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. 3. data based on design simulation and/or technology characteristics, not tested in production. 4. c l1 (resp.c l2 ) is load capacitance on osc1 (resp. osc2) pin. 5. r s is the equivalent serial resistance of the crystal or ceramic resonator. symbol parameter conditi ons min typ 1) max unit t c(inst) instruction cycle time 2 4 12 t cpu f cpu =8mhz 250 500 1500 ns t v(it) interrupt reaction time 2) t v(it) = d t c(inst) +10 10 22 t cpu f cpu =8mhz 1.25 2.75 m s symbol parameter condi tions min typ max unit v osc1h osc1 input pin high level voltage see figure 73 0.7xv dd v dd v v osc1l osc1 input pin low level voltage v ss 0.3xv dd t w(osc1h) t w(osc1l) osc1 high or low time 3) 15 ns t r(osc1) t f(osc1) osc1 rise or fall time 3) 15 r obp oscillator bypass exteranl resistor 1 k w symbol parameter conditio ns min max unit f osc oscillator frequency 4 16 mhz c l1 ,c l2 load capacitance 4) r s =100 w 5) 12 21 pf t start oscillator start-up time depends on resonator quality. a typical value is 10ms v osc1l v osc1h t r(osc1) t f(osc1) t w(osc1h) t w(osc1l) 90% 10%
st72311r, st72511r, st72512r, st72532r 139/164 12.6 memory characteristics subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. 12.6.1 ram and hardware registers 12.6.2 eeprom data memory 12.6.3 eprom program memory notes: 1. minimum v dd supply voltage without losing data stored into ram (in in halt mode or under reset) or into hardware registers (only in halt mode). guaranteed by construction, not tested in production. 2. the data retention time increase when the t a decreases. 3. data based on reliability test results and monitored in production. 4. data given only as guidelines. symbol parameter conditi ons min typ max unit v rm data retention mode 1) halt mode (or reset) 1.6 v symbol parameter conditi ons min typ max unit t prog programming time (for 1 up to 16 bytes at a time) -40 c t a +85 c10 ms -40 c t a +125 c15 t ret data retention 3) t a = +55 c 2) 20 years n rw write erase cycles 3) t a = +25 c 300 000 cycles symbol parameter conditions min typ max unit w erase uv lamp lamp wavelength 2537? 15 watt.sec /cm 2 t erase erase time 4) uv lamp is placed 1 inch from the device window without any interposed filters 15 20 min t ret data retention 3) t a =+55 c 2) 20 years
st72311r, st72511r, st72512r, st72532r 140/164 12.7 emc characteristics susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the leds). n esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. n ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re- sumed. figure 74. emc recommended star network power supply connection 2) notes: 1. data based on characterization results, not tested in production. 2. the suggested 10nf and 0.1 m f decoupling capacitors on the power supply lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as possible to the device power supply pins. other emc recommen- dations are given in other sections (i/os, reset, oscx pin characteristics). symbol parameter condition s neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-2 -1 1 kv v fftb fast transient voltage burst limits to be ap- plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25 c, f osc = 8mhz conforms to iec 1000-4-4 -4 4 v dd v ss 0.1 m f 10nf v dd st72xxx v ssa v dda 0.1 m f power supply source st7 digital noise filtering external noise filtering
st72311r, st72511r, st72512r, st72532r 141/164 emc characteristics (cont'd) 12.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, re- fer to the an1181 st7 application note. 12.7.2.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega- tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 75 and the following test sequences. human body model test sequence c l is loaded through s1 by the hv pulse gener- ator. s1 switches position from generator to r. a discharge from c l through r (body resistance) to the st7 occurs. s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence c l is loaded through s1 by the hv pulse gener- ator. s1 switches position from generator to st7. a discharge from c l to the st7 occurs. s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st7 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. r (machine resistance), in series with s2, en- sures a slow discharge of the st7. absolute maximum ratings figure 75. typical equivalent esd circuits notes: 1. data based on characterization results, not tested in production. symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25 c 2500 v v esd(mm) electro-static discharge voltage (machine model) t a = +25 c tbd st7 s2 r=1500 w s1 high voltage c l = 100pf pulse generator st7 s2 high voltage c l = 200pf pulse generat or r=10k~10m w s1 human body model machine model
st72311r, st72511r, st72512r, st72532r 142/164 emc characteristics (cont'd) 12.7.2.2 static and dynamic latch-up n lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 st7 application note. n dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 76. for more details, refer to the an1181 st7 application note. electrical sensitivities figure 76. simplified diagram of the esd generator for dlu notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec- ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. symbol parameter conditions class 1) lu static latch-up class t a = +25 c t a = +85 c a a dlu dynamic latch-up class v dd = 5.5v, f osc = 4mhz, t a = +25 c tbd r ch =50m w r d =330 w c s = 150pf esd hv relay dischar ge tip discharge return connection generator 2) st7 v dd v ss
st72311r, st72511r, st72512r, st72532r 143/164 emc characteristics (cont'd) 12.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. the stress generally affects the circuit el- ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro- tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al- lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 77 and figure 78 for standard pins and in figure 79 and figure 80 for true open drain pins. standard pin protection to protect the output structure the following ele- ments are added: a diode to v dd (3a) and a diode from v ss (3b) a protection device between v dd and v ss (4) to protect the input structure the following ele- ments are added: a resistor in series with the pad (1) a diode to v dd (2a) and a diode from v ss (2b) a protection device between v dd and v ss (4) figure 77. positive stress on a standard pad vs. v ss figure 78. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path
st72311r, st72511r, st72512r, st72532r 144/164 emc characteristics (cont'd) true open drain pin protection the centralized protection (4) is not involved in the discharge of the esd stresses applied to true open drain pads due to the fact that a p-buffer and diode to v dd are not implemented. an additional local protection between the pad and v ss (5a & 5b) is implemented to completly absorb the posi- tive esd discharge. multisupply configuration when several types of ground (v ss ,v ssa , ...) and power supply (v dd ,v dda , ...) are available for any reason (better noise immunity...), the structure shown in figure 81 is implemented to protect the device against esd. figure 79. positive stress on a true open drain pad vs. v ss figure 80. negative stress on a true open drain pad vs. v dd figure 81. multisupply configuration in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path path to avoid (5a) (5b) in v dd v ss (1) (2b) (4) out v dd v ss (3b) main path (3b) (3b) v dda v ssa v dda v dd v ss back to back diode between grounds v ssa
st72311r, st72511r, st72512r, st72532r 145/164 12.8 i/o port pin characteristics 12.8.1 general characteristics subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. figure 82. two typical applications with unused i/o pin notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor (see figure 82). data based on design simulation and/or technology characteristics, not tested in production. 5. the r pu pull-up equivalent resistor is based on a resistive transistor. this data is based on characterization results, not tested in production. 6. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv i l input leakage current v ss v in v dd 1 m a i s static current consumption 4) floating input mode 200 r pu weak pull-up equivalent resistor 5) v in = v ss v dd =5v 60 240 k w c io io pin capacitance 5 pf t f(io)out output high to low level fall time 2) c l =50pf between 10% and 90% 25 ns t r(io)out output low to high level rise time 2) 25 t w(it)in external interrupt pulse time 6) 1t cpu 10k w unused i/o port st72xxx 10k w unused i/o port st72xxx v dd
st72311r, st72511r, st72512r, st72532r 146/164 i/o port pin characteristics (cont'd) 12.8.2 output driving current subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. figure 83. typical v ol at v dd =5v (standard) figure 84. typical v ol at v dd =5v (high-sink) figure 85. typical v dd -v oh at v dd =5v notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced must always respect the absolute maximum rating specified in section 12.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . symbol parameter conditio ns min max unit v ol 1) output low level voltage for a standard i/o pin when 8 pins are sunk at same time (see figure 83) v dd =5v i io =+5ma 1.3 v i io =+2ma 0.4 output low level voltage for a high sink i/o pin when 4 pins are sunk at same time (see figure 84) i io =+20ma 1.3 i io =+8ma 0.4 v oh 2) output high level voltage for an i/o pin when 8 pins are sourced at same time (see figure 85) i io =-5ma v dd -2.0 i io =-2ma v dd -0.8 02468 iio [ma] 0 0.2 0.4 0.6 0.8 1 1.2 1.4 (vdd=5v) vol [v] ta=-40 c ta=25 c ta=85 c ta=125 c 010203040 iio [ma] 0 0.5 1 1.5 2 (vdd=5v) vol [v] ta=-40 c ta=25 c ta=85 c ta=125 c -8 -6 -4 -2 0 iio [ma] 0 0.5 1 1.5 (vdd=5v) vdd-voh [v] ta=-40 c ta=25 c ta=85 c ta=125 c
st72311r, st72511r, st72512r, st72532r 147/164 12.9 control pin characteristics 12.9.1 asynchronous reset pin subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. figure 86. typical application with reset pin 5) 12.9.2 v pp pin subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. figure 87. two typical applications with v pp pin 7) notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching levels. based on characterization results, not tested. 4. the r on pull-up equivalent resistor is based on a resistive transistor. this data is based on characterization results, not tested in production. 5. the reset network protects the device against parasitic resets, especially in a noisy environment. 6. data based on design simulation and/or technology characteristics, not tested in production. 7. when the in-circuit programming mode is not required by the application v pp pin must be tied to v ss . symbol parameter condit ions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 400 mv r on weak pull-up equivalent resistor 4) v in = v ss v dd =5v 20 60 k w t w(rstl)out generated reset pulse duration watchdog reset source 1 m s t h(rstl)in external reset pulse hold time 20 m s reset v dd watchdog reset st72xxx lvd reset internal reset control r on 0.1 m f v dd 0.1 m f v dd 4.7k w external reset circuit symbol parameter conditio ns min max unit v il input low level voltage 6) v ss 0.2 v v ih input high level voltage 6) v dd -0.1 12.6 v pp st72xxx 4.7k w programming tool v pp st72xxx
st72311r, st72511r, st72512r, st72532r 148/164 12.10 timer peripheral characteristics subject to general operating condition for v dd ,f o- sc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (outpu compare, input capture, external clock, pwm output...). 12.10.1 watchdog timer 12.10.2 8-bit pwm-art auto-reload timer 12.10.3 16-bit timer symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 12,288 786,432 t cpu f cpu =8mhz 1.54 98.3 ms symbol parameter condit ions min typ max unit t res(pwm) pwm resolution time 1t cpu f cpu =8mhz 125 ns f ext art external clock frequency 0 f cpu /2 mhz f pwm pwm repetition rate 0 f cpu /2 res pwm pwm resolution 8 bit v os pwm/dac output step voltage v dd =5v, res=8-bits 20 mv symbol parameter condit ions min typ max unit t w(icap)in input capture pulse time 1 t cpu t res(pwm) pwm resolution time 2t cpu f cpu =8mhz 250 ns f ext timer external clock frequency 0 f cpu /4 mhz f pwm pwm repetition rate 0 f cpu /4 mhz res pwm pwm resolution 16 bit
st72311r, st72511r, st72512r, st72532r 149/164 12.11 communications interface characteristics 12.11.1 spi - serial peripheral interface subject to general operating condition for v dd ,f o- sc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (ss, sck, mosi, miso). figure 88. spi slave timing diagram with cpha=0 3) notes: 1. data based on design simulation and/or characterisation results, not tested in production. 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends on the i/o port configuration. 3. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . symbol parameter conditio ns min max unit f sck 1/t c(sck) spi clock frequency master f cpu =8mhz f cpu /128 0.0625 f cpu /4 2 mhz slave f cpu =8mhz 0 f cpu /2 4 t r(sck) t f(sck) spi clock rise and fall time see i/o port pin description t su(ss) ss setup time slave 120 ns t h(ss) ss hold time slave 120 t w(sckh) t w(sckl) sck high and low time master slave 100 90 t su(mi) t su(si) data input setup time master slave 100 100 t h(mi) t h(si) data input hold time master slave 100 100 t a(so) data output access time slave 0 120 t dis(so) data output disable time slave 240 t v(so) data output valid time slave (after enable edge) 120 t h(so) data output hold time 0 t v(mo) data output valid time master (before capture edge) 0.25 t cpu t h(mo) data output hold time 0.25 ss input sck input cpha=0 mosi input miso output cpha=0 t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t v(so) t a(so) t su(si) t h(si) msb out msb in bit6 out lsb in lsb out see note 2 cpol=0 cpol=1 t su(ss) t h(ss) t dis(so) t h(so) see note 2 bit1 in
st72311r, st72511r, st72512r, st72532r 150/164 communications interface characteristics (cont'd) figure 89. spi slave timing diagram with cpha=1 1) figure 90. spi master timing diagram 1) notes: 1. measurement points are done at cmos levels: 0.3xv dd and 0.7xv dd . 2. when no communication is on-going the data output line of the spi (mosi in master mode, miso in slave mode) has its alternate function capability released. in this case, the pin status depends of the i/o port configuration. ss input sck input cpha=0 mosi input miso output cpha=0 t w(sckh) t w(sckl) t r(sck) t f(sck) t a(so) t su(si) t h(si) msb out bit6 out lsb out see cpol=0 cpol=1 t su(ss) t h(ss) t dis(so) t h(so) see note 2 note 2 t c(sck) hz t v(so) msb in lsb in bit1 in ss input sck input cpha=0 mosi output miso input cpha=0 cpha=1 cpha=1 t c(sck) t w(sckh) t w(sckl) t h(mi) t su(mi) t v(mo) t h(mo) msb in msb out bit6 in bit6 out lsb out lsb in see note 2 see note 2 cpol=0 cpol=1 cpol=0 cpol=1 t r(sck) t f(sck)
st72311r, st72511r, st72512r, st72532r 151/164 communications interface characteristics (cont'd) 12.11.2 sci - serial communications interface subject to general operating condition for v dd ,f o- sc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (rdi and tdo). 12.11.3 can - controller area network interface subject to general operating condition for v dd ,f o- sc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). symbol parameter conditions standard baud rate unit f cpu accuracy vs. standard prescaler f tx f rx communication frequency 8mhz ~0.16% conventional mode tr (or rr)=64, pr=13 tr (or rr)=16, pr=13 tr (or rr)= 8, pr=13 tr (or rr)= 4, pr=13 tr (or rr)= 2, pr=13 tr (or rr)= 8, pr= 3 tr (or rr)= 1, pr=13 300 1200 2400 4800 9600 10400 19200 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 hz extended mode etpr (or erpr) = 13 38400 ~38461.54 ~0.79% extended mode etpr (or erpr) = 35 14400 ~14285.71 symbol parameter condit ions min typ max unit t p(rx:tx) can controller propagation time 60 ns
st72311r, st72511r, st72512r, st72532r 152/164 12.12 8-bit adc characteristics subject to general operating condition for v dd ,f osc , and t a unless otherwise specified. figure 91. typical application with adc notes: 1. unless otherwise specified, typical data are based on t a =25 c and v dd -v ss =5v. they are given only as design guide- lines and are not tested. 2. when v dda and v ssa pins are not available on the pinout, the adc refer to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k w ). data based on characterization results, not tested in production. 4. the stabilization time of the ad converter is masked by the first t load . the first conversion after the enable is then always valid. symbol parameter conditions min typ 1) max unit f adc adc clock frequency 4 mhz v ain conversion range voltage 2) v ssa v dda v r ain external input resistor 15 3) k w r adc internal input resistor 1.5 k w c adc internal sample and hold capacitor 6 pf t stab stabilization time after adc enable f cpu =8mhz, f adc =4mhz 0 4) m s t load sample capacitor loading time 1 4 m s 1/f adc t conv hold conversion time 2.250 9 m s 1/f adc ainx st72xxx c io 0.1 m f v dd i l 1 m a v t 0.6v v t 0.6v r adc c adc 0.1 m f sampling switch v ain r ain v dda v ssa 0.1 m f v dd 1k w
st72311r, st72511r, st72512r, st72532r 153/164 adc characteristics (cont'd) adc accuracy with v dd =5.0v figure 92. adc accuracy characteristics notes: 1. data based on characterization results over the whole temperature range, monitored in production. 2. adc accuracy vs. negative injection current: for i inj- =0.8ma, the typical leakage induced inside the die is 1.6 m a and the effect on the adc accuracy is a loss of 1 lsb for each 10k w increase of the external analog source impedance. this effect on the adc accuracy has been observed under worst-case conditions for injection: - negative injection - injection to an input with analog capability, adjacent to the enabled analog input -at5vv dd supply, and worst case temperature. symbol parameter conditions min max unit |e t | total unadjusted error 2) f cpu =8mhz, f adc =4mhz 1) 1.5 lsb e o offset error 2) -1 1 e g gain error 2) -0.5 0.5 |e d | differential linearity error 2) 1 |e l | integral linearity error 2) 1 e o e g 1 lsb ideal 1lsb ideal v dda v ssa 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa
st72311r, st72511r, st72512r, st72532r 154/164 13 package characteristics 13.1 package mechanical data figure 93. 64-pin thin quad flat package figure 94. 64-pin epoxy thin quad flat package note : a qualification or volume production of devices using epoxy packages (eso/edil/eqfp) is not authorized it is expressly specified that qualification and/or volume production of devices using the package e.... in any applications is not authorized. usage in any application is strictly restricted to development purpose. similar devices are available in plastic package mechanically compatible to the epoxy package for qualification and volume production.o dim mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 e 0.80 0.031 k 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 64 nd 16 ne 16 l1 l k dim mm inches min typ max min typ max a 2.40 0.095 a1 0.60 0.024 b 0.25 0.38 0.50 0.010 0.015 0.020 e 15.80 16.00 16.20 0.622 0.630 0.638 e1 12.20 12.35 12.50 0.480 0.486 0.492 e 0.80 0.031 g 13.10 0.515 l 0.50 0.020 l1 1.10 0.043 ? n 0.35 0.013 ? p 1.10 0.043 number of pins n 64 (4x16) etqfp 64 l1 l ? n b ? p e g a1 a
st72311r, st72511r, st72512r, st72532r 155/164 13.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d =p int +p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j =t a +p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) tqfp64 60 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c
st72311r, st72511r, st72512r, st72532r 156/164 13.3 soldering and glueability information recommended soldering information given only as design guidelines. figure 95. recommended wave soldering profile (with 37% sn and 63% pb) figure 96. recommended reflow soldering oven profile (mid jedec) recommended glue for smd plastic packages dedicated to molding compound with silicone: n heraeus: pd945, pd955 n loctite: 3615, 3298 250 200 150 100 50 0 40 80 120 160 time [sec] temp. [ c] 20 60 100 140 5 sec cooling phase (room temperature) preheating 80 c phase soldering phase 250 200 150 100 50 0 100 200 300 400 time [sec] temp. [ c] ramp up 2 c/sec for 50sec 90 sec at 125 c 150 sec above 183 c ramp down natural 2 c/sec max tmax=220+/-5 c for 25 sec
st72311r, st72511r, st72512r, st72532r 157/164 13.4 package/socket footprint proposal to solder the tqfp64 device directly on the appli- cation board, or to solder a socket for connecting the emulator probe, the application board should provide the footprint described in figure 97. this footprint allows both configurations: n direct tqfp64 soldering n yamaichi ic149-064-008-s5 socket soldering to plug either the emulator probe or an adaptor board with an tqfp64 clamshell socket. this socket is not compatible with tqfp64 package. figure 97. tqfp64 device and emulator probe compatible footprint table 27. suggested list of tqfp64 socket types package / probe adaptor / socket reference socket type tqfp64 enplas otq-64-0.8-02 open top yamaichi ic51-0644-1240.ks-14584 clamshell emu probe yamaichi ic149-064-008-s5 smc detai l e b * sk: plastic socket overall dimensions. dim mm inches min typ max min typ max b 0.35 0.45 0.50 0.014 0.018 0.020 e 20.80 0.819 e1 14.00 0.551 e3 11.90 12.00 12.10 0.468 0.472 0.476 e 0.75 0.80 0.85 0.029 0.031 0.033 sk* 26 1.023 number of pins n 64 (4x16) e e1 e3 e e1 e3 socket sk sk
st72311r, st72511r, st72512r, st72532r 158/164 14 device configuration and ordering information each device is available for production in user pro- grammable versions (otp) as well as in factory coded versions (rom). otp devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code sup- plied by the customer. this implies that otp de- vices have to be configured by the customer using the option bytes while the rom devices are facto- ry-configured. 14.1 option bytes the option byte allows the hardware configuration of the microcontroller to be selected. the option byte has no address in the memory map and can be accessed only in programming mode (for example using a standard st7 program- ming tool). the default content of the otp is fixed to ffh. this means that all the options have a1o as their default value. in masked rom devices, the option bytes are fixed in hardware by the rom code (see option list). user option byte bit 7:6,4 = reserved , must always be 1. bit 5 = reserved , must always be 0. bit 3 = fmp full memory protection this option bit allows the protection of the software contents against piracy (program or data). when the protection is activated, read-out of the eprom or data eeprom contents is prevented by hard- ware. 0: read-out protection enabled 1: read-out protection disabled bit 2 = reserved , must always be 1 bit 1 = wdg halt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode bit 0 = wdg sw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) user option byte 7 0 fmp wdg halt wdg sw default value 111 1 1111
st72311r, st72511r, st72512r, st72532r 159/164 14.2 device ordering information and transfer of customer code customer code is made up of the rom contents and the list of the selected options (if any). the rom contents are to be sent on diskette, or by electronic means, with the s19 hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly completed option list appended. the stmicroelectronics sales organization will be pleased to provide detailed information on con- tractual points. figure 98. rom factory coded device types figure 99. otp user programmable device types device package temp. range xxx / code name (defined by stmicroelectronics) = lvd disabled s= lvd enabled 1= standard 0 to +70 c 6= industrial -40 to +85 c 7= automotive -40 to +105 c 3 = automotive -40 to +125 c t= tqfp st72311r6, st72311r7, st72311r9 st72511r6, st72511r7, st72511r9 st72512r4 st72532r4 x device package temp. range = lvd disabled s= lvd enabled 1= standard 0 to +70 c 6= industrial -40 to +85 c 7= automotive -40 to +105 c 3 = automotive -40 to +125 c t= tqfp st72t311r6, st72t311r7, st72t311r9 st72t511r6, st72t511r7, st72t511r9 st72t512r4, st72t532r4 x
st72311r, st72511r, st72512r, st72532r 160/164 transfer of customer code (cont'd) microcontroller option list customer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............................. contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone n ............................. reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references device: [ ] st72311r9 [ ] st72511r9 [ ] st72512r4 [ ] st72311r7 [ ] st72511r7 [ ] st72532r4 [ ] st72311r6 [ ] st72511r6 package: [ ] tqfp64 temperature range: [ ] 0 cto+70 c []-40 cto+85 c []-40 c to + 105 c []-40 c to + 125 c oscillator source selection: [ ] quartz crystal/ceramic resonator [ ] external clock watchdog selection: [ ] software activation [ ] hardware activation watchdog reset on halt [ ] disabled [ ] enabled readout protection: [ ] disabled [ ] enabled lvd reset [ ] disabled [ ] enabled: comments : supply operating range in the application: notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
st72311r, st72511r, st72512r, st72532r 161/164 14.3 development tools stmicroelectronics offers a range of hardware and software development tools for the st7 micro- controller family. full details of tools available for the st7 from third party manufacturers can be ob- tain from the stmicroelectronics internet site ? http//st7.st.com. third party tools n actum n bp n cosmic n cmx n data i/o n hitex n hiware n isystem n kanda n leap tools from these manufacturers include c compli- ers, emulators and gang programmers. stmicroelectronics tools four types of development tool are offered by st, all of which connect to a pc via a parallel (lpt) port: note : 1. in situ programming (isp) interface for flash devices. table 28. stmicroelectronics development tools in-circuit emulation programming capability 1) software included st7 development kit yes. (same features as hds2 emulator but no trace/ logic analyzer) yes (dip packages only) st7 cd rom with: st7 assembly toolchain wgdb7 powerful source level debugger for win 3.1, win 95 and nt) c compiler demo versions st realizer for win 3.1 and win 95. windows programming tools for win 3.1, win 95 and nt st7 hds2 emulator yes, powerful emulation fea- tures including trace/ logic an- alyzer no st7 programming board no yes (all packages) supported products development kit hds2 emulator programming board st72311r6, st72311r7, st72311r9 st72511r6, st72511r7, st72511r9 st72512r4 st72532r4 st7mdt2-dvp2 st7mdt2-emu2b st7mdt2-epb2/eu st7mdt2-epb2/us st7mdt2-epb2/uk
st72311r, st72511r, st72512r, st72532r 162/164 15 st7 generic application note to get more information to get the updated information on that product please refer to stmicroelectronics web server. ? http://st7.st.com/ identification description programming and tools an912 a simple guide to development tools an985 executing code in st7 ram an986 using the st7 indirect addressing mode an987 st7 in-circuit programming an988 starting with st7 assembly tool chain an989 starting with st7 hiware c an1039 st7 math utility routines an1064 writing optimized hiware c language for st7 example drivers an969 st7 sci communication between the st7 and a pc an970 st7 spi communication between the st7 and e prom an971 st7 i c communication between the st7 and e prom an972 st7 software spi master communication an973 sci software communication with a pc using st72251 16-bit timer an974 real time clock with the st7 timer output compare an976 driving a buzzer using the st7 pwm function an979 driving an analog keyboard with the st7 adc an980 st7 keypad decoding techniques, implementing wake-up on keystroke an1017 using the st7 usb microcontroller an1041 using st7 pwm signal to generate analog output (sinusoid) an1042 st7 routine for i c slave mode management an1044 multiple interrupt sources management for st7 mcus an1045 st7 software implementation of i c bus master an1047 managing reception errors with the st7 sci peripheral an1048 st7 software lcd driver an1048 st7 timer pwm duty cycle switch for true 0% or 100% duty cycle product optimization an982 using ceramic resonators with the st7 an1014 how to minimize the st7 power consumption an1070 st7 checksum selfchecking capability product evaluation an910 st7 and st9 performance benchmarking an990 st7 benefits versus industry standard applications examples an1086 st7 / st10u435 can-do solutions for car multiplexing
st72311r, st72511r, st72512r, st72532r 163/164 16 summary of changes description of the changes between the current release of the specification and the previous one. revision main changes date 2.1 - section 8.4 olow power modeso on page 42 and section 8.5 ointerruptso on page 42 added in section 8 oi/o portso on page 38. - section 10.2.5 olow power modeso on page 53 and section 10.2.6 ointerruptso on page 53 added in section 10.2 omain clock controller with real time clock timer (mcc/rtc)o on page 52. - esd absolute maximum rating modified in section 12.2 on page 132. - emc characteristics corrected in section 12.7 on page 140. feb-00
st72311r, st72511r, st72512r, st72532r 164/164 notes: information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain sweden - switzerland - united kingdom - u.s.a. http:// www.st.com

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